Hello I'm in a first year digital logic class and have just had a test. There was a bonus question that I got partial marks for but am really wondering how I could have gotten full marks. We don't get the tests back to see what was right or wrong, just the mark. I will show what was asked and what i did. It has to do with designing a circuit with the fewest number of logic gates to complete.

The question went something along the lines of "using three toggle switches (A, B, C) design a circuit using only logic gates (and or nand nor xor xnor not) or latches or flip flops (SR, D, JK) that turn on 3 lights. If zero or one switch is on turn on light 1. If 2 switches are on turn on light 2. If all three switches are on turn on lights 1,2 and 3. Do this using the fewest number of gates possible. Inverters (nots) do not count towards your total, use as many as you want. You can not split the outputs from any logic gate

I started by creating a truth table
A B C Lt1 Lt2 Lt3
0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 0 1 0
1 1 0 0 1 0
1 1 1 1 1 1

I created 3 karnaugh maps and came up with the following boolean expressions
A'B'+A'C'+B'C'+ABC = Lt1
AB+AC+BC= Lt2
ABC = Lt3

(I hope I'm remembering this correctly)

Putting this all together I came up with 10 gates as written above (8 and gates and 2 or gates, using 3 inverters)

I'm not very good with flip flops or latches etc. Could there be a way of reducing the above further using these? I received half marks for this bonus question.

Help! I'm stumped! I've spent all weekend dwelling on this!!

 

The constraint that you can't split the outputs is strange, but okay.

Think about the logic for light 1. It needs to be on if (all three switches are off) OR (an odd number of switches are on). You can save a gate here.

Similarly, the logic for light 2 can be stated as it needing to be on if (an even number of switches is on) AND (all three switches are NOT off). But I don't think that will save you a gate.

 

Thank you for the reply. I've been thinking about what you said and working with a couple other equally stumped classmates and I think we've got it about simplified as much as possible. I must have drawn this circuit out 200 times or more in the last week but this is what I came up with.

Now if anyone thinks they can reduce this further I'm all ears. I've gotten it down to 6 gates and I think all requirements met.

I don't know how I could have possibly gotten these full bonus marks on this exam. I don't think anyone did in the class. I guess that's why they were bonus...

So is this it? Can it be reduced further? At this point I'm about done with this question. Honestly I'm sick of it!

 

Multi-input (i.e., > 2 inputs) XOR gates are usually not considered as basic gates, because the basic two-input definition of "exclusive-OR" doesn't extend to multiple inputs. But if you change the definition to odd-parity, then you can extend it to an arbitrary number of inputs.

Now, with an XOR (or XNOR gate) if you change ANY input, the output changes state. Is that what you want? What will your first light do when all of the inputs, {A,B,C}, are HI?

My solution only used 2-input XOR/XNOR gates. If I use multi-input, I think I would have been at 7 gates.

 

Wouldn't the first light be ON if all switches on?
I entered this circuit into Logic.ly and it seems to confirm that all three lights would indeed be on if all three switches on.
I find these multi input xor gates confusing.

 

Wouldn't the first light be ON if all switches on?
I entered this circuit into Logic.ly and it seems to confirm that all three lights would indeed be on if all three switches on.
I find these multi input xor gates confusing.

My bad -- I referred back to your first post and only saw that it was supposed to be on if zero or one switch was on. Missed the later part about it also being on if all three switches are on (even though my suggestion was based on the observation that 1 and 3 are both odd numbers). LT1 works.

But look at LT2. Notice that it is the same circuit as LT1 except that it has the AND output coming it as well. But that will only affect the circuit when it is HI which is the single case when all the switches are on. Ask yourself what LT2 will be when all of the switches are off.

 

My bad -- I referred back to your first post and only saw that it was supposed to be on if zero or one switch was on. Missed the later part about it also being on if all three switches are on (even though my suggestion was based on the observation that 1 and 3 are both odd numbers). LT1 works.

But look at LT2. Notice that it is the same circuit as LT1 except that it has the AND output coming it as well. But that will only affect the circuit when it is HI which is the single case when all the switches are on. Ask yourself what LT2 will be when all of the switches are off.

My drawing above is a little rough.
The difference between circuit 1 and 2 other than the AND gate is that there is a XNOR instead of and XOR. I *think* if all switches are off LT2 will also be off...?

 

Hello compuNERD:

Why You Do Not think in decimal notation:
Looking on Your True Table, above.
L1 Will turn ON in: 0 OR 1 OR 2 OR 4 OR 7.
L2 Will turn ON in: 3 OR 5 OR 6 OR 7.
L3 Will turn ON in: 7.

This is he same:
L1=(A&B&C)+(B’&C’)+(A’&C’)+(A’&B’)
L2=(B&C)+(A&C)+(A&B)
L3=(A&B&C)

'( )' Means a Gate.
If contains '&' Is AND Gate,
If contains '+' Is OR Gate.
X’ means complement of X.
Etc.
The amount of Inputs for each Gates depends of the terms inside the parenthesis sign.

For example:
For L1 You need:
1 4-inputs OR Gate.
1 3-inputs AND Gate.
3 3-inputs AND Gate
3 inverters to complement A, B, C.

Now, normally A is the LSB (Least Significant Bit)
But you have them backwards.
Normally this is so:
A LSB.
B.
C MSB.
Although the acronym actually only gives a name to the BIT in question.

Note:
Although simulators for electronic circuits has X-NOR or X-OR gates with more than 2 inputs, I think it can not commercially available.

 

Hello compuNERD:

Why You Do Not think in decimal notation:
Looking on Your True Table, above.
L1 Will turn ON in: 0 OR 1 OR 2 OR 4 OR 7.
L2 Will turn ON in: 3 OR 5 OR 6 OR 7.
L3 Will turn ON in: 7.

This is he same:
L1=(A&B&C)+(B’&C’)+(A’&C’)+(A’&B’)
L2=(B&C)+(A&C)+(A&B)
L3=(A&B&C)

'( )' Means a Gate.
If contains '&' Is AND Gate,
If contains '+' Is OR Gate.
X’ means complement of X.
Etc.
The amount of Inputs for each Gates depends of the terms inside the parenthesis sign.

For example:
For L1 You need:
1 4-inputs OR Gate.
1 3-inputs AND Gate.
3 3-inputs AND Gate
3 inverters to complement A, B, C.

Now, normally A is the LSB (Least Significant Bit)
But you have them backwards.
Normally this is so:
A LSB.
B.
C MSB.
Although the acronym actually only gives a name to the BIT in question.

Note:
Although simulators for electronic circuits has X-NOR or X-OR gates with more than 2 inputs, I think it can not commercially available.

LOL!! Thanks for the reply but did you read the OP?

 

My drawing above is a little rough.
The difference between circuit 1 and 2 other than the AND gate is that there is a XNOR instead of and XOR. I *think* if all switches are off LT2 will also be off...?

Okay. Let's take it from the top from your circuit. Maybe that way I will stop reading it incorrectly.

A|B|C|D=(A+B+C)'|E=(ABC)|LT1=XOR(A,B,C,D)|LT2=XNOR(A,B,C,D,E)|LT3=E
0|0|0|1|0|1|0|0
0|0|1|0|0|1|0|0
0|1|0|0|0|1|0|0
0|1|1|0|0|0|1|0
1|0|0|0|0|1|0|0
1|0|1|0|0|0|1|0
1|1|0|0|0|0|1|0
1|1|1|0|1|1|1|1

And I think this fulfills your requirements.

Good job.