Hi All,

I'm new to the forums but it would be great to get some help from you for a new project that I already have in the planning stages. I'm a professional software developer, with experience including real-time software development and low level programming in assembly language. But I'm relatively new to digital electronics and thus there are some subjects I am not that confident about.

I have been watching (and learning) from the excellent videos on simple CPU design by Ben Eater, such as this one

Basically the video shows a D-type Edge triggered Flip Flop with some logic to prevent Inputs to be feed to the Flip Flop if we do not want to (starting at 3:35). The circuit the author of the video proposes, is identical to the 74LS173 as seen in this datasheet file : http://www.ti.com/lit/ds/symlink/sn74ls173a.pdf . In fact, he ends using two 74LS173 to implement a 8 bit register. Let's call it Circuit 1.

This is fine, however I do not understand why this additional logic is required for it to work. (Note that I am not asking about the buffered tri-state outputs but just the inputs). My understanding is that we could just use a regular D-type Edge triggered Flip Flop such as this http://www.ti.com/lit/ds/symlink/sn74ls273.pdf and then just input the IC clock with a circuit combining the clock with the Input enable signal like the one shown in the attachment. Circuit 2.

My question is: is there any fundamental working difference between the two circuits, provided that the input enable (G1) is provided well in advance to the clock pulse (CLK)?

Thanks


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Hi joanlluch, as far as I can see you are correct and there is no real difference between the 2. The LS173 just has some additional functionality, tri-state output and hold. The 273 is a simpler IC. You often get this with logic ICs - several flavours of the same thing, often you will actually find that you cant find anywhere to buy some of the ICs from, so it limits your choice.

 

Your hand drawn circuit is what is known as a "gated clock". This is generally a "bad thing". It moves you into the realm of asynchronous logic design which is a world filled with critical races and circuits that are sensitive to timing hazards. In short, you are off the edge of the map and there be demons in those waters.

Consider your G1 signal. If it is deasserted while the clock is HI, then if the logic producing that signal produces a glitch, your chip now sees a clock pulse.

Gated clocks should be avoided in the extreme unless you are willing and prepared to undertake the much more demanding design tasks to ensure that your circuit is hazard free and that all critical races are guaranteed to always be resolved in a safe manner over the entire operating range of the circuit -- and this is going to often involve taking into account the actual PCB routing details.

Generally not a world you want to work in unless there's a damn good reason (and damn good reasons to work there DO exist).

 

Hi WBahn,

Thank you for your reply, I understand what you say and in some way I intuitively suspect that putting a gate on a clock signal can lead to trouble.

However, just to clarify, please allow me to expose the intended timing of the application. The global logic of the system is not asynchronous, but fully synchronous. The system clock is a symmetric square wave, I mean same time on and off (please correct me if that's not the right technical term, as I'm not English native). The G1 signal will never change next to the raising of the system clock.

In particular, the G1 signal is indirectly driven by a circuit that updates it on the falling edge of the signal clock. G1 is kept constant until the next falling edge of the clock. The G1 update will of course have some delay due to logic circuitry delays, or may have some short living glitches due to the complexity of the logic setting it, but all changes will be always near the falling edge of the clock signal. By the time the raising edge of the clock arrives, the G1 signal will be already stable and fixed, as well as the input bus values. At this time (raising edge) the value on the bus will be copied to the register as shown in the schematics above (both Circuit 1 and 2).

In fact, I the described sequence of events I understand that is identical to those of a simple CPU. The G1 signal and the input bus values are kept stable during a entire clock cycle (from falling edge to falling edge), which is phased by 1/2 cycle respect the time the clock raising edge actually updates the register.

So, given this way of working, can still Circuit 2 create glitches, while Circuit 1 will not?.

Thanks