Under what circumstances could a 74HC(T)74 fail to transfer the D input to the Q output on the positive-going edge of the clock input? I have pin 2 (D input) and pin 4 (Set) tied to +5v and I apply a clock to pin 3. Mostly it works, but sometimes my logic analyser shows the clock pulse applied correctly but no change in the Q and NOT Q outputs. The clock pulses are about 3uS long. See the attached jpegs; the correct operation shows three clock pulses with corresponding changes in the Q outputs. The other image shows what goes wrong; three clock pulses but only two changes of Q states.
Any ideas would be much appreciated.
Paul.
Any ideas would be much appreciated.
Paul.
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