74HC74 timing issues

Thread Starter

Paul57

Joined Apr 12, 2011
19
Under what circumstances could a 74HC(T)74 fail to transfer the D input to the Q output on the positive-going edge of the clock input? I have pin 2 (D input) and pin 4 (Set) tied to +5v and I apply a clock to pin 3. Mostly it works, but sometimes my logic analyser shows the clock pulse applied correctly but no change in the Q and NOT Q outputs. The clock pulses are about 3uS long. See the attached jpegs; the correct operation shows three clock pulses with corresponding changes in the Q outputs. The other image shows what goes wrong; three clock pulses but only two changes of Q states.

Any ideas would be much appreciated.

Paul.
 

Attachments

MrChips

Joined Oct 2, 2009
21,281
Are you doing simulation or testing real chips?

Here are some possibilities that first come to mind:

1) Supply voltage out of range.
2) Supply voltage is noisy.
3) Vcc and GND not properly decoupled.
4) CLOCK signal faulty, i.e. voltage, timing, rise time, fall time, noise.
5) Chip is faulty.
 

Papabravo

Joined Feb 24, 2006
13,910
The circumstances that can cause this behavior are called setup and hold violations. A setup criteria is one that says the input must be "setup" (and not change) for some time t prior to the clock edge. A hold criteria is one that says the input must be "held" for some time t after the clock edge. These two conditions are associated with metastability, where the output can be undefined for some period of time surrounding the clock edge.

You did not provide a schematic of your setup, so I have to ask how the other F-F in the package is wired, and more importantly how are the set and preset inputs wired. Lastly I need to ask about bypass capacitors -- you do have some -- right?
 

Papabravo

Joined Feb 24, 2006
13,910
Is the D input present sufficiently ahead of the clock to satisfy the setup and hold times?
He said the D input was wired to +5V, so I think the answer is yes,

I notice a glicth, ath the clock edge, on the Q output at the beginning of the trace in the first image -- where did it com from?
There is also an unlabeled trace in the second image -- what is it?
 

Thread Starter

Paul57

Joined Apr 12, 2011
19
Thanks for all the replies. It's a real circuit and I do have several decoupling caps. The D input (pin 2) is permanently tied to +5v so that should satisfy the setup and hold requirements. Pin 4 (preset) is not used so is tied to +5v. I will check for noise on the reset signal.

Thanks for all the suggestions.

Paul.
 

djsfantasi

Joined Apr 11, 2010
6,497
The timing diagrams you attached show another signal which you haven’t described. @Papabravo raised a question about it. How is your Reset signal wired? What drives it? What is high and low on it? And by how, I mean physically how it’s wired. Is there a long wire, for example?

UPDATE: Our posts crossed. If Reset is tied high, what are you showing on your timing diagrams. And to be clear, I’m making an assumption that preset (not on my datasheet) is really reset.
 

Papabravo

Joined Feb 24, 2006
13,910
You are using CLEAR to reset the FF at some point after clocking in the "1" on the D-input. How is that signal generated and what about the other part in the package?
 

Thread Starter

Paul57

Joined Apr 12, 2011
19
The CLEAR/RESET signal (applied to pin 1) is generated via an RC network from a pin on a PC printer port. The signal from the PC is a bit long (6uS or so) so the RC network ensures a short pulse.

The second half of the HCT74 is unused. Pin 13 is tied to +5v and pins 12, 11 and 10 are grounded.

I have attached a circuit diagram of part of my project.
 

Attachments

MrChips

Joined Oct 2, 2009
21,281
That is what I suspected.
Take a look at the /RESET signal with a fast oscilloscope.
Try a different way of generating the /RESET signal (such as a monostable multivibrator) to see if that is the cause of the problem.
 

Papabravo

Joined Feb 24, 2006
13,910
You do not under any circumstances want to connect a capacitor to a CMOS input. It will create very sharp input spikes on the RESET input, and in fact that is what you are seeing. Find another way to implement the function. For example, just get rid of the capacitor and control the pin directly from an I/O port.

One more thing -- isn't your data latch backwards for a printer port?
 
Last edited:

Thread Starter

Paul57

Joined Apr 12, 2011
19
Looks like noise on the reset pin was the issue. I have just added a series 220 ohm resistor and everything is working nicely. I will come up with a more elegant solution in due course.

The reason for the CR network is that the PC can't generate a pulse narrower than about 6uS, and if the reset pin is low, Q is held low (NOT BUSY) so the device could send more data before the PC is ready.

The data latch is correct. That part of the circuit is for transfer INTO the printer port.

Thanks for all your help.
 

Papabravo

Joined Feb 24, 2006
13,910
Because you cannot establish a defined DC level on the CLEAR input, you will always have a weak link here. It may work today, or tomorrow, but it will fail at some point. Your choice to engage in sloppy design practice, just be aware that what you have is a differentiator. What comes out will be proportional to the derivative of what goes in. These spikes from the may cause the voltage on the CLEAR pin to exceed Vcc. This could be bad for 74HC74. The derivative of a step function is a delta function. Your best bet is to send a triangle pulse to it, and it will turn into a pulse.
 
Last edited:
Top