I know how to make 5 bit 2's complement adder and 5 bit 1's complement adder separately can someone give mi idea how to make adder that depending on signal can add works as 5 bit 2's complement or 5 bit 1's complement adder

 

This is getting a bit old. You post a question, don't show your work and when asked to show your work you simply start a new thread with essentially the same question, apparently hoping to bait someone into doing your work for you. Doesn't work like that.

SHOW YOUR WORK!

You say that you know how to do a 2's comp and a 1's comp adder separately. Okay. Fine. Let's see them.

Then describe what you see as the key differences and similarities they share that you might exploit to convert one into the other based on a control signal input.

 

So what are the differences and similarities between the two?

Are you trying to implement an adder, or an adder/subtractor? Do you need overflow detection?

Do you understand how both of those circuits that you copied from somewhere actually implement addition and subtraction?

 

I know how they work the differences between them is that 2's complemetn adder just make complement of the imput and ignore the last carry and 1's complement add that carry to the sum what i want to do is to connect them in one and yes i also need overflow detection

A two's complement adder doesn't do anything to the input. Now, a two's complement subtractor does. That's why I asked if you need to make an adder or an adder/subtractor.

The 1' complement circuit you posted doesn't do overflow detection, yet you said that you need overflow detection.

In general, if I have two signals and sometimes -- determined by a control signal -- I want to see one of them and other times I want to see the other, what is a straightforward way to accomplish that?

 

I need adder only and i remove XOR gates form the 2's complement adder and the overflow detector for the 1's complement is the same as overflow detector for 2's complement correct me if i'm wrong and i make them in one circuit with one AND gate that has the control signal and the last carry as an input and the output goes to the first carry that is modification of the 2's complement adder without using 1's commplement adder )

I'm not even going to try to follow this. Please show a schematic of what you are proposing.