The problem is to do a full adder module with data input X, Y, carry input Cin and Sum output S and carry output Cout. It says to design using 3-8 decoder, which i already did, but now I need to design it using 4-1 multiplexers, do i need to find stuff like Minterm and S1,2,3,4 ??. How can I go about solving this??
Can you write the truth table of the Full Adder, for starters? We can talk more after you do that. The theory behind that paper is that after you find the boolean expression of a function F(A,B,Cin), you use inputs A and B to drive the MUX's select pins and use the following functions to drive the input pins: For Input 00 -> F(0,0,Cin) For Input 01 -> F(0,1,Cin) For Input 10 -> F(1,0,Cin) and so on... P.S. You actually have to evaluate F(0,0,Cin) for those values.