Just a simple question... if you connect up a 2 7418 encoder to together to form a 16-4 encoder...

There are are 4 outputs. But I noticed that the GS output will always be 0 in all cases that any of the switches are toggled.

Does that mean that the GS out is redundant for values 0-7, and should only be considered when looking at value 8-15?

 

I didn't know you could actually do that. Can you show us a schematic?

 

I think you wire up the Enable on one and the NOT Enable on the other as the D (bit 4) address.

 

OK, but the OP wrote "encoder" and mentioned 4 outputs, then described a circuit implemented with "decoders". So which is it? Are you trying to make a 16-4 encoder? How can you do that with "decoder" chips?

 

I think you wire up the Enable on one and the NOT Enable on the other as the D (bit 4) address.

Can't do that, I need the output of the enable of the second 7418 to enable the 1st 7418. Then I connect all the corresponding outputs together, A0 to A0, A1 to A1, GS to GS using AND. This is the answer my tutor gave me. It seems to work for number 8 and above because.

If you toggle the 2nd encoder...

The E0 output will be high... deactivating the first, causing the output to be all 1111, so lets say u choose 14, which will be the 6th output on the second encoder. GS(MSB) is 0 and 6 is 001, so 0001 and 1111 AND 0001 = 0001(Active Low) = 1110 = 14.

However, if the 2nd encoder is not toggled, the 1st encoder works like a normal encoder and the 2nd encoder gives 1111 for all its output... so like before if toggle 6, taking GS(MSB) is 0, and 6 is 001 and 1111 AND 0001 = 0001(Active Low) = 1110 = 14? Unless... the 0 is not looked at for the 2st encoder... den we see it as 6.

 

OK, but the OP wrote "encoder" and mentioned 4 outputs, then described a circuit implemented with "decoders". So which is it? Are you trying to make a 16-4 encoder? How can you do that with "decoder" chips?

Oops, I meant 7418

 

That's because the post originally said LS138
Never heard of the 7418

 

Oops, I meant 7418

What is that IC? None of my TTL manuals have it.

 

What is that IC? None of my TTL manuals have it.

Typo again, 74148.

 

Oops, I meant 7418

The only chip I know of that is described as an encoder would be the 74xx147 or 74xx148. Are those the chips that you are referring to? (EDIT: I see the correction). We used them as interrupt priority encoders, but never in cascade mode. So a schematic would be really helpful.

 

ABC and GS would be the outputs... and the inputs are connected to toggled switches. E0 of the 1st Encoder is not connected.

 

I'm not sure this arrangement will do what you want it to do. You are aware that a "priority encoder" will set its outputs according to the "highest priority input". For example if switch 15 is the highest priority switch then switches 0 throuh 14 are effectively invisible, that is their values are a complete "don't care". Also when switch 15 is released then the output will go to the highest priority active switch. Is this the behavior that you want or do you have something else in mind.

BTW since you are working with complicated logic, how is it that you don't have a proper schematic capture package, or even a logic template to draw clear and concise drawings, but are using PC Paint for a purpose that it is not suited to.

 

I'm not sure this arrangement will do what you want it to do. You are aware that a "priority encoder" will set its outputs according to the "highest priority input". For example if switch 15 is the highest priority switch then switches 0 throuh 14 are effectively invisible, that is their values are a complete "don't care". Also when switch 15 is released then the output will go to the highest priority active switch. Is this the behavior that you want or do you have something else in mind.

BTW since you are working with complicated logic, how is it that you don't have a proper schematic capture package, or even a logic template to draw clear and concise drawings, but are using PC Paint for a purpose that it is not suited to.

Becoz I am just a Uni student? And I am not even an engineering student and I am obligated to take up logic circuits just for some general knowledge on circuits? My focus is mainly on alogorithm and programming.

Well, that ans was given to my tutor, and yeah... the rest will be invisible but if the 2nd encoder is activated, the 1st encoder outputs all always go high 1111... and lets take Switch 14 for the second encoder...which is 0001 since the output is inverse... so 1111 + 0001 is 0001 which is 14 if u inverse it 1110... So to say the GS is for padding the MSB.

But it doesn't seem to work for 0-7 becos... GS is always 0... so there will always be a 1 infront... man... these uni questions dun make sense.

 

OK, but part of the problem is that you need an accurate and informative schematic in order to debug and troubleshoot any complex circuit. It needs to be complete and it needs to have pin numbers, and there just are not any shortcuts. Not in the university and certainly not in industry.

On page 13 of the following datasheet is the circuit you require.
http://focus.ti.com/lit/ds/symlink/sn74148.pdf

Notice the subtle difference. The MSB of the encoded output is the GS from the higher bank of inputs. It is zero if there are no inputs on the high bank and 1 otherwise. The AND of GS-low and GS-high gives the priority flag which says there is an active input.

I was confused by your drawing because it was not completely labeled.