101 sequence detector using Verilog

Thread Starter


Joined Apr 15, 2011

I was watching this video which shows how to implement overlapping 101 sequence detector using Moore and Mealy state machines:

I'm only interested in Moore state machine implementation.

The figure below has been captured from the mention video. I need your help to understand the diagram. In the diagram, I've drawn arrows myself to clarify input and output for my own understanding.

I'd really appreciate it if you could help me with the queries below.

Question 1:
If the input to state S0 is 0, it doesn't change. If the input is 1, it goes to state S1.

If the input to S1 is 1, it doesn't change. Shouldn't it go back to state S0 when the input is 1?

Question 2:
If the input to S1 is 0, it goes to next state S2. If the input is 0, S2 goes back to S0 which makes sense.

If the input to S3 is 0, it goes back to S2. And if the input is 1, in goes back to S1.

I think since it's an overlapping detector therefore S3 should go back to S2 after getting 0 as an input. In case of a non-overlapping detector for 101 sequence, S3 should go back to S0 after getting 0 as an input, do I have it correct?


Question 3:
This question is about the code for Moore 101 sequence detector taken from the mentioned video.

How do I find how many states I need? In the given case, there are four states from S0 to S3. What's the general rule to find the number of states needed for such problems? Could you please help me? Thanks, in advance!