full bridge

Hello, I have used a Zener diode-based voltage divider to create a negative bias for a gate driver supply but I noticed that the series resistor is getting too hot!! This is the process of how I designed this supply: P = (Freq × Qg × Delta[Vgs] × N ), Where P is the average power, Freq is the...

Hello all, I am trying to build a hardware setup for a PEC9 inverter. Since it has more switches and a different configuration than a regular half/full bridge (meaning no high and low side), I didn't know how to connect the gate driver's power side pins (VDD/VSS) since usually in a half-bridge...

Hello, I need to design a linear regulated supply to power an dac output stage based on op amp. It must be a negative + ground + positive one. The problem I encounter is that I don't know wich topology to select between the first and second arrangement. I suppose that the first one induce a...

Hello, I have been designing a full bridge single phase inverter. It's bus voltage is 20Vdc. There is enough of dead-time for Vgs signals between the-same-leg mosfets and they are driven by gate driver. I checked Vgs signals for the-same-leg mosfets and saw the dead-time clearly. At each power...