Hi! I have made two truth tables but have a hard time writing the boolean expression in order to be able to see how to draw a diagram of the state machine using logic gates and D elements. I am using Moore FSM and below are the instrctions and my truth tables. WOuld really appreciate help on how...
I'm doing a Finite state machine of a elevator using verilog. The elevator contain four states: IDLE, MOVING, ERROR, ALERT
* IDLE: When the elevator is stopped.
* ERROR: When the elevator's weigth limit is exceeded.
* MOVING: When the elevador leaves the current floor and start moving across...
When designing the state machine, do I need to derive a separate output equation for each of the five outputs, or can I group them into the UP signals (U1, U2), the DOWN signals (D1, D2), and the NOGO signal?
Assuming this FSM is a Mealy type, what would be the structure of the truth table...
My college homework ask me to design a simplified traffic light controller that switches the lights at a street intersection (North-South street N-S and East-West street E-O). The controller's input is a button called **PASS**, which is activated by pedestrians when they wish to cross one of the...
I am working on a traffic light control system for an intersection with a **main road (Vp)** and a **secondary road (Vs)**, using:
- **Vehicle detectors**:
- **Dp** (main road).
- **Ds** (secondary road).
- **Pedestrian buttons**:
- **Pp** (to cross the main road).
- **Ps**...
I need to design an FSM sequence detector that activates when it detects the sequences 01011 and 00101. The problem is that I don't know how, for example, when state s3 receives the value 0 and reaches 010, to make s3 transition to 001 if it receives a 1. This is the design I made:
I need...