Flip flops - latches

hey guys. i have a question. when we talk about JK flip flops, does it imply that since its a flip flop, they are all edge triggered? can latches be edge triggered? or a latch becomes a flip flop as soon as we add a clock to it?

You have to be careful how you define what is a latch.

Some people use the word latch to be a generic term to mean any type of stable state machine. Hence a flip-flop is also a latch. A SET-RESET flip-flop may be considered a "latch" even though there is no clock.

Generally, all flip-flops are edge triggered. A master-slave flip-flop will capture the data on the leading edge but will not change its output state until the trailing edge of the clock is received.

The narrow definition of a latch is a transparent latch where the output follows the input when the clock input is active (high for positive logic). The data is "latched" on the trailing edge (high-to-low transition for positive logic).

In this definition, a latch needs a clock or enable signal.

I have seen some D type latches (dual or 8 units inside the IC) where the latch is a level trigger.

AFAIK a J/K flip flop is intrinsically edge triggered. Edge trigger is part of the JK definition.

thanks guys.