Hi,
I have a question related to the undefined region of the TTL logic.
I have the setup presented in the attached image.
My question is: how can I handle the region of undefined TTL signal received from another device (when the TTL signal is between 0.4V and 2.6V and we are not certain what the output will be at Vout) so that it will always produce a defined output state at Vout (ex: when the TTL signal is in the undefined region the output will always be low).
What is the common practice for this? Should I assume that the received TTL signal will not go into the undefined region (except for transition from low to high)?
Thank you,
Buzai
I have a question related to the undefined region of the TTL logic.
I have the setup presented in the attached image.
My question is: how can I handle the region of undefined TTL signal received from another device (when the TTL signal is between 0.4V and 2.6V and we are not certain what the output will be at Vout) so that it will always produce a defined output state at Vout (ex: when the TTL signal is in the undefined region the output will always be low).
What is the common practice for this? Should I assume that the received TTL signal will not go into the undefined region (except for transition from low to high)?
Thank you,
Buzai
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