TTL undefined region of operation

Discussion in 'General Electronics Chat' started by buzaiandras, May 30, 2012.

  1. buzaiandras

    Thread Starter Member

    Jul 18, 2011
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    Hi,

    I have a question related to the undefined region of the TTL logic.
    I have the setup presented in the attached image.
    My question is: how can I handle the region of undefined TTL signal received from another device (when the TTL signal is between 0.4V and 2.6V and we are not certain what the output will be at Vout) so that it will always produce a defined output state at Vout (ex: when the TTL signal is in the undefined region the output will always be low).

    What is the common practice for this? Should I assume that the received TTL signal will not go into the undefined region (except for transition from low to high)?

    Thank you,

    Buzai
     
  2. MrChips

    Moderator

    Oct 2, 2009
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    All gates have to make the transition from one defined region to the other defined region and in doing so must move through the undefined region.

    In reality, there is no undefined region since one only has to choose a single threshold voltage below which we call it a zero and above we call it a one.

    In the case of an open-collector output or open-drain output as you have shown, the transistor will simply make a transition from being in the OFF state to being ON.

    So you simply ignore the fact that the gate voltage is changing from below 0.4V to greater than 2.6V, especially since this is going to happen in less than 1ns.

    A totem-pole output is more problematic because the output of the gate becomes biased in the linear region. This allows huge currents to flow and can present a phenomenon called "ground bounce" creating huge spikes on the supply and ground rails.
    That is why we put bypass capacitors on the supply lines close to the Vcc and GND pins.
     
    Last edited: May 30, 2012
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  3. WBahn

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    Mar 31, 2012
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    The thing to keep in mind is that the 0.4V and 2.6V values are specified limits. Without looking at the TTL I/O spec (meaning I could get a detail slightly wrong, so don't take this as gospel), what these values tell you is that if the output of the TTL gate is supposed to be LO and if you are not asking it to sink more than the specified maximum current, that you can count on all properly operating (i.e., undamaged and properly powered) gates having proper input signals to be at or below 0.4V. Most will be significantly lower, but all of them will be at least that low. The same is true for the other limit, namely that you can rely on all properly operating gates that have proper input signals and that are not being asked to supply more than the specificed maximum current, to be no lower than 2.6V. Again, most will be considerably higher than that, but none will be below that.

    As a designer, it is your job to ensure that each TTL gate is properly powered, has proper input signals, and is properly loaded. If you do those three things, then it is reasonable for you to assume that the outputs will behave properly and that the time spent in the transition zone will be no more than what is spec'ed in the data sheet.

    For your circuit, you should develop a similar spec (it can be real simple) for your I/O characteristics. Since your input is coming from a TTL output, you should be safe if your circuit satisfies the TTL input specification. That will say that any input voltage below a certain level (I seem to recall it is about 0.8V) must be recognized and acted upon as a logic LO while any voltage above a certain level (I seem to recall it is about 1.8V) must be recognized and acted upon as a logic HI. In general, you also want to make sure that the current requirements in either state meet the input spec, but that is not a concern in this case give that your load is just a FET gate (unless you are operating at really high speed). The only other thing you need to do is determine what the maximum amount of time the input to your circuit can take to transition between LO and HI (in either direction) without causing problems and compare that to the maximum time that a TTL output can take.

    You want to do something similar for your circuit's output. The "spec" that you make it meets has to be reasonable for the circuit that it is driving.
     
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  4. buzaiandras

    Thread Starter Member

    Jul 18, 2011
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    Thank you for your responses.

    I forgot to mention that Vout will be connected directly to a MCU.

    My concern is for the situation when the TTL signal from the other device (on which I have no control) falls into the undefined region (0.4V ... 2.6V). For example lets assume that the device is broken and it only outputs voltages on the undefined region of TTL. Some values from the undefined region will produce a HI and some values will produce a LOW on Vout.

    Since the MCU will control other devices based on the HI or LOW value of Vout I need to make sure that the values from the undefined region all defaults to the same known state (either HI or LOW)

    So how can I handle this situation? Are there any common practices for this kind of situations?

    I apologize if it is not clear what am I talking about :(.

    Thank you,

    Buzai
     
  5. THE_RB

    AAC Fanatic!

    Feb 11, 2008
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    The input pin of your MCU should be a "schmidt trigger" or "ST" type. These have clearly defined switching points like <1v to go LO and >3.5v to go HI. In between these 2 points the output will remain the same as it was.

    If you MCU does not have an ST input you can buy a logic chip that is a ST buffer or ST inverter and put that between your suspect logic output and the MCU input.
     
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  6. buzaiandras

    Thread Starter Member

    Jul 18, 2011
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    Thank you for the suggestion. I'll try that.
    One more question. Is this a common practice? Are they any other solutions to this problem?
    I ask because I try to learn more about this kind of circuits.

    Thank you,

    Buzai
     
  7. MrChips

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    Oct 2, 2009
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    Every gate to gate interface would suffer the same risk of failure.
    You cannot possibly create a fault tolerant system that covers every possible failure condition at the gate level.

    If you are designing a mission critical system with a high level of fault tolerance then you have to look at a triple redundancy system where the fault and recovery analysis is done at a functional system level.

    The bottom line is, I am not aware of any case where the designer has to be concerned with the sub-ns transition through the undefined logic region.

    We have discussed in another thread recently the use of pull-up or pull-down resistors when there is concern that the output gate may inadvertently go into a high-impedance state, or open-collector or open-drain mode.
     
    Last edited: May 31, 2012
  8. WBahn

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    If you are going to be concerned about the TTL gate producing the input signal to your circuit failing, then you have to ask about what if your little RTL (resistor-transistor logic) inverter fails?

    If your circuit is just driving an input of a MCU, why are you using your circuit at all as opposed to a logic inverter? The gain on an inverter is sufficiently high that the region of operation that results in undefined outputs is very small (a few millivolts). You just don't know where, within the datasheets performance specifications, that region lies.

    In other words, pick a hex inverter IC out of the box and it might recognize anything below 1.37V as a LO and everything above 1.43V as a HI. Another gate in that same package may change state around 1.5V. Tomorrow those voltages may be different because the temperature is different or the supply voltage is slightly different. But the actual range for which the output voltage fails to meet spec will be quite small.
     
  9. buzaiandras

    Thread Starter Member

    Jul 18, 2011
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    I am sorry but I am not sure I follow. My setup is already an inverter. You are saying that a dedicated logic inverter IC will give a smaller error margin?

    Thank you,

    Buzai
     
  10. WBahn

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    QUite possibly. Remember, the people that designed an inverter IC took a lot of time (probably tens of thousands of dollars worth) to make a really good inverter.

    But it would be good to do the sims and find out. Now, to get a meaningful SIM, your TTL part has to have a model that behaves accurately during the transition period. Many digital parts do not have good detailed models for this kind of behavior.

    But you can actually build the circuits and use an oscilloscope to get a feel for the typical behavior. What you want to do, if you can, is put in a triangle wave into the input (but a sine wave will work, as well) and then use the X-Y mode to see the output versus input characteristic. You should see a high voltage on the left of the screen and a low voltage on the right with a transition zone inbetween. The width of this zone is the uncertainty region you are interested in. Change the frequency of the input waveform and you will probably see the zone tighten up as you go from real low frequencies to moderate frequencies and then not change a whole lot after that.
     
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  11. Ron H

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    Apr 14, 2005
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    Your chosen transistor is not be guaranteed to turn on with Vgs=2.6V anyway.
    74HCT14 would almost certainly do what you want, but if the specs on that scare you, you can make a Schmitt trigger with arbitrary threshold levels by using an LM393 and four resistors. If you need a schematic for that, let us know.
     
  12. davebee

    Well-Known Member

    Oct 22, 2008
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    To answer another question you asked a few times, yes, this is a common problem, especially as there are getting to be so many cases where 3.3 volt devices need to feed a digital signal to 5 volt systems, and 5 volt devices feed 3.3 volt MCUs, and TTL logic levels are mixed with CMOS logic levels.

    If I'm unsure how any two devices will work together, I have often just stuck a Schmidt trigger between them to clean up the signal, just in case.
     
  13. buzaiandras

    Thread Starter Member

    Jul 18, 2011
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    Thank you all for your help.

    @Ron H: A schematic would be more than welcomed :)

    Could you please detail this a little more?
    According to my calculations (for the setup presented in the picture) to get a LOW at Vout (0.8V for the MCU TTL input) I only need a drain current (Id) of about 420-450 uA.
    In the datasheet I saw that for the worst case (T = -55C, Figure 2 from the datasheet) at 2.5V I will have a drain current of about 400mA for Vds =30V.
    I assumed that if at Vgs=2.5V and Vds = 30V I get a drain current of 400mA than at Vgs=2.5V and Vds=0.8V I would get a drain current of around 10mA which is still enough to get a LOW on Vout.
    I may be (very) wrong; I am new to FETs and FET datasheets :). But I hope to learn :)
    Are my calculations and assumptions wrong?

    Thank you,

    Buzai
     
  14. Ron H

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    Fig. 2 is the wrong place to look. Fig. 2 (and all the other figures) show typical characteristics.
    I always look at the Rds(on) worst case spec, which is Rds=0.2Ω @ Vgs=5V. It is not spec'ed below Vgs=5V.
    Vgs(th) is 2V max, but this is with Ids=250uA and Vds=2V.
    Your circuit will probably work with TTL signals, but it certainly will not guarantee a logic level out, when the input level is unknown. This requires infinite gain, which implies a Schmitt trigger.
     
  15. WBahn

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    A Schmitt trigger won't do this, either. The Schmitt trigger will prevent bouncing due to noise about the transition point, but each transition is still going to have a region in which the input signal could be such that the output state is at an intermediate value. I'm not sure that this region is even any narrower than a comparable non-Schmitt trigger input, though I suspect it probably is. In either case, however, the region is small. The big difference with a Schmitt trigger is that, with a normal input, the device could continue giving problems for some time by just staying near the region and straying back and forth through it. With a Schmitt trigger, it would have to stay near this region on one side and not venture too far into it since the first time it does, even under noise, it will transition and the threshold will change.

    My guess is that most practical circuits can count on noise keeping a Schmitt triggered device from behaving poorly in response to a poorly behaving input (note that we aren't talking about an input that is flailing).
     
  16. Ron H

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    Come again? A Schmitt trigger doesn't have intermediate states.
    I think I would set the thresholds at 0.4V and 2.6V. If the input wanders across this range, I don't see another solution.
     
  17. WBahn

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    Just like a normal input, as the input voltage rises from a solid LO toward the lower threshold, at some point the output will start to fall but will not be committed to the transition. If the input voltage is lowered, then the output voltage will rise back up. Now, the positive feedback makes this range very small, but it is still there. Also, if the thresholds are chosen well, the output will still be firmly in the prior state when the commitment point is reached to transition to the other state. The narrower the hysteresis, the more likely this is to become an issue.

    Assuming I've got my numbers correct for TTL, I definitely would NOT set my limits at 0.4V and 2.6V. Vihmin is 2.0V and Vilmax is 0.8V. This means that any voltage at the input at or below 0.8V must be treated as a logic LO while any voltage at or above 2.0V must be treated as a logic HI. So the widest you could set them would be there, at 0.8V and 2.0V. But you need to set them even narrower than that because you have to allow for component and power supply tolerances and possibly other effects such as temperature. To meet spec, your thresholds have to be inside that window over all of those variations. Without running the numbers, I would probably target my nominal thresholds at 1.0V to 1.2V and 1.6V to 1.8V.
     
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