Voltage Level Shifter

[lmartinez]

I was hoping I could get assistance understanding the given discrete circuit above rather than utilizing an op amp. As a learning process I want to understand how the discrete circuit works. Please advice

[t_n_k]

Hi Imartinez,

Here's my perspective on the circuit operation ....

If the MCU output is ~+5V, Q1 will turn on. i.e. Q1 will saturate and hence the base drive at Q2 will be low (Q1 Vce_sat ~0.1V) - causing Q2 to be turned off. Q3 is a source follower and will be turned on with the gate drive virtually at 12V (via R3) with Q2 off. Q3 source voltage will be ~12V with Q3 Vds low and R4 taking virtually the full 12V supply.

With the MCU output at 0V, Q1 will be turned off, Q2 will be driven on (saturated) via the base current drive through R2 and D1. Hence Q3 gate drive will be low (Q2 Vce sat~0.1V) and source follower Q3 will be off. Output will be 0V as no current flows in Q3 via R4.

So you have a logic level shift from (TTL level ?) 0-5V to 0-12V.

One issue may the logic output levels for the MCU. If MCU logic low is substantially higher than 0V, there will be tendency for Q1 to turn on - possibly upsetting the anticipated circuit condition.

I'm not sure of the purpose of diode D1 - presumably it's there to ensure Q2 wont turn on unless Q1 is definitely off. Perhaps this relates to the matter of MCU logic levels I mentioned above.

[lmartinez]

Originally Posted by t_n_k

Hi Imartinez,

Here's my perspective on the circuit operation ....

If the MCU output is ~+5V, Q1 will turn on. i.e. Q1 will saturate and hence the base drive at Q2 will be low (Q1 Vce_sat ~0.1V) - causing Q2 to be turned off. Q3 is a source follower and will be turned on with the gate drive virtually at 12V (via R3) with Q2 off. Q3 source voltage will be ~12V with Q3 Vds low and R4 taking virtually the full 12V supply.

With the MCU output at 0V, Q1 will be turned off, Q2 will be driven on (saturated) via the base current drive through R2 and D1. Hence Q3 gate drive will be low (Q2 Vce sat~0.1V) and source follower Q3 will be off. Output will be 0V as no current flows in Q3 via R4.

So you have a logic level shift from (TTL level ?) 0-5V to 0-12V.

One issue may the logic output levels for the MCU. If MCU logic low is substantially higher than 0V, there will be tendency for Q1 to turn on - possibly upsetting the anticipated circuit condition.

I'm not sure of the purpose of diode D1 - presumably it's there to ensure Q2 wont turn on unless Q1 is definitely off. Perhaps this relates to the matter of MCU logic levels I mentioned above.

Your explanation is well understood. I am still intrigued by the purpose of the diode. With regards to the frequency response of this circuit I will do the math and go from there. Thank you very much for your assistance

[Ron H]

The source follower output will never reach 12V, due to the fact that the MOSFET has a threshold voltage. The output voltage will probably get to around ≈10-11V, depending on the threshold.

The reason I suggested getting the gain from the op amp is that you said this was the output load.