Voltage Level Shifter

Discussion in 'General Electronics Chat' started by lmartinez, Nov 3, 2009.

  1. lmartinez

    Thread Starter Active Member

    Mar 8, 2009
    224
    6
    Hello everyone,

    I would like to know if anyone can help me understand how the voltage level shifter works for the attached circuit. I found it in one of the forum posts. I am looking for a level shifter that can function at speeds of up to 500kHz. It will be driven by a micro controller with a square wave output of 5 volts peak. As a result, i am looking at the attached circuit. Please advise and thank you in advance.
     
  2. silvrstring

    Active Member

    Mar 27, 2008
    159
    0
    Do you have to use that particular design? It's much easier to explain and understand a voltage level shifter made with an opamp.
     
  3. lmartinez

    Thread Starter Active Member

    Mar 8, 2009
    224
    6

    A high speed Operational Amplifier would be great! Please advice:)
     
  4. tibbles

    Active Member

    Jun 27, 2008
    249
    3
    hi martinez, while silvrstring is getting back,
    re your original circuit, im fairly new but i think q2 is actually the "level shifter", but in this configuration it will also invert the signal, so q1 is used as another invertor to maintain the logic.
    the diode keeping 12volt from preceeding stages?
    but i have been wrong....
     
    Last edited: Nov 3, 2009
  5. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    What output levels are you looking for? What will the load be?
     
  6. lmartinez

    Thread Starter Active Member

    Mar 8, 2009
    224
    6
    :)
    The input voltage to the level shifter is 5 volts dc( to consumed less than 20mAmps) and the output voltage is to be 12 Volts DC. The input resistance of the load connected to the Voltage Level Shifter is to be in the range of mega ohms(an op amp buffer). Those are the parameters which I will be working with. PLEASE ADVICE.....
     
  7. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    Is your input a logic signal, with 0 volts and 5 volts as the two logic levels? If so, do you want the corresponding output levels to be 0 volts and 12 volts?
    The circuit you posted will not do that.
     
  8. lmartinez

    Thread Starter Active Member

    Mar 8, 2009
    224
    6
    Yes, those are the two logic levels for the input and output voltages I would like have.

    What if I do not use Q3 and R4 and take the output voltage at the transistor's, Q2, collector? Will that work? Will the circuit I posted function properly at switching frequencies of 500Khz? If not, can you provide a circuit which will do what I am looking for.. Thank you
     
  9. MikeML

    AAC Fanatic!

    Oct 2, 2009
    5,450
    1,066
    Does one end of the external load have to be grounded? If yes, you need a high-side driver.

    Is the load capacitive in nature? If yes, you need a push-pull driver to both charge and discharge the capacitance.
     
  10. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    What is your actual application? Why do you need an op amp buffer? If you do, why can't you just use a buffer with gain=2.4?
    Post a schematic (a block for the level shifter will be sufficient), and include the op amp buffer, and whatever else is downstream from it.
     
  11. lmartinez

    Thread Starter Active Member

    Mar 8, 2009
    224
    6
    I was hoping I could get assistance understanding the given discrete circuit above rather than utilizing an op amp. As a learning process I want to understand how the discrete circuit works. Please advice
     
  12. t_n_k

    AAC Fanatic!

    Mar 6, 2009
    5,448
    782
    Hi Imartinez,

    Here's my perspective on the circuit operation ....

    If the MCU output is ~+5V, Q1 will turn on. i.e. Q1 will saturate and hence the base drive at Q2 will be low (Q1 Vce_sat ~0.1V) - causing Q2 to be turned off. Q3 is a source follower and will be turned on with the gate drive virtually at 12V (via R3) with Q2 off. Q3 source voltage will be ~12V with Q3 Vds low and R4 taking virtually the full 12V supply.

    With the MCU output at 0V, Q1 will be turned off, Q2 will be driven on (saturated) via the base current drive through R2 and D1. Hence Q3 gate drive will be low (Q2 Vce sat~0.1V) and source follower Q3 will be off. Output will be 0V as no current flows in Q3 via R4.

    So you have a logic level shift from (TTL level ?) 0-5V to 0-12V.

    One issue may the logic output levels for the MCU. If MCU logic low is substantially higher than 0V, there will be tendency for Q1 to turn on - possibly upsetting the anticipated circuit condition.

    I'm not sure of the purpose of diode D1 - presumably it's there to ensure Q2 wont turn on unless Q1 is definitely off. Perhaps this relates to the matter of MCU logic levels I mentioned above.
     
  13. lmartinez

    Thread Starter Active Member

    Mar 8, 2009
    224
    6
    Your explanation is well understood. I am still intrigued by the purpose of the diode. With regards to the frequency response of this circuit I will do the math and go from there. Thank you very much for your assistance
     
  14. Ron H

    AAC Fanatic!

    Apr 14, 2005
    7,050
    656
    The source follower output will never reach 12V, due to the fact that the MOSFET has a threshold voltage. The output voltage will probably get to around ≈10-11V, depending on the threshold.

    The reason I suggested getting the gain from the op amp is that you said this was the output load.
     
Loading...