Why Verilog-AMS came into Analog and Mixed Signal Design Verification


The term "Analog and Mixed Signal design verification" means verifying analog and mixed signal designs concurrently. Hence, the traditional verification flow e.g. stand alone analog verification or stand alone digital verification is not sufficient to verify Mixed Signal ICs in which analog and digital blocks are distributed throughout the chip.

The standard Verilog code cannot mimic the electrical behavior of an analog block. Hence, the requirement is to come up with a solution that integrates both analog and digital interaction in a tightly coupled fashion.

Verilog-A can mimic the circuit behaviors with electrical accuracy and uses analog solver. Hence, it takes longer time to simulate with Verilog-A based behavioral model.

Therefore, the need is to have a continuous domain with digital solver in order to speed up simulation time and also which can mimic analog behaviors. Verilog-AMS came into picture in AMS verification.

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figure 1: Verilog-AMS structure

Verilog-AMS is a super set of Verilog and Verilog-A as shown in Figure 1.

"wreal" - a new data type has been introduced in Verilog-AMS. wreal based modeling uses digital solver and hence simulation speeds up. It also minimizes convergence issues and mimic analog behavior. Hence, it is continuous in value and discrete in time.

Verilog-AMS lets designers of analog and mixed-signal systems and integrated circuits create and use modules which encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components. The behavior of each module can be described mathematically in terms of its ports and external parameters applied to the module. The structure of each component can be described in terms of interconnected sub-components. These descriptions can be used in many disciplines such as electrical, mechanical, fluid dynamics, and thermodynamics. For continuous systems, Verilog-AMS
is defined to be applicable to both electrical and non-electrical systems description. It supports conservative and signal-flow descriptions by using the concepts of nets, nodes, branches, and ports as terminology for these descriptions. The solutions of analog behaviors which obey the laws of conservation fall within the generalized form of Kirchhoff’s Potential and Flow Laws (KPL and KFL). Both of these are defined in terms of the quantities (e.g., voltage and current) associated with the analog behaviors.

Some basic features of Verilog-AMS:

  • Signals of both analog and digital types can be declared in the same module
  • Increasing verification of analog performance at the top level of the design.
  • Significantly reducing the top level simulation time.
  • Creating an appropriate environment for chip architecture design.
Basic requirement for Verilog-ams code simulation, is to have a Verilog-ams code file with file extension of .vams, and a testbench also with the extension of .vams

Why Verilog-AMS?
  • Faster implementation as compared to C ( or FORTRAN)
  • Multiple simulators support:
    • Analog Device: Adice,...
    • Motorola/Freescale: Mica,...
    • Cadence: Spectre, Ultrasim,...
    • Mentor Graphics: Eldo,...
    • Synopsys: Nanosim, HSIM,...
    • Agilent: ADS & ICCap,...
    • Silvaco: SmartSpice & UTMOST,...

How can I convert electrical signal into wreal signal?

The following example describes an event-driven electrical to wreal conversion module where the absdelta() function is used to determine when the electrical input signal is converted to a wreal output signal.
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Verilog-AMS has the potential to shorten design cycles and increase success of more mixed signal ICs.

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Babun Pal
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