SoftStart Expo

Below diagrammed is the active 'inrush-limiter' for application to our unregulated linear low EMF PSU -- Inasmuch as this circuit varies from 'standard' 555 'technique' (especially as regards timing cap discharge) A cursory circuit description follows the image.



Please note that U3 and its associated circuitry provide the 'ballasting-delay' at start-up and following mains interruptions of one or more cycles' duration, whereas the circuitry of U1 detect interruptions/absence of mains power --- Both U1 and U2 are configured as monostable 'one-shots' featuring external 'rapid reset' circuitry.


To begin:

Note -- for convenience only the following discussion assumes F(mains) = 60Hz

1)
-
K1 is a small mains transformer featuring a 120V primary and twin 12V, 1A secondaries. -- Note: K1 operates directly from the mains and, hence, is not controlled by the Variac.

-R2 loaded by the 'back-to-back diode action' of D1 and the b-e junction of Q1 'clip' the sinusoidal power signal (from L3) to ± V(f) of the respective semiconductors (i.e. ≈ ±0.7V).

-Owing to the highly abbreviated, 'peri-crossing' locus of the 'sample interval', acceptably abrupt slopes are achieved -- Whereas saturation and cutoff of Q1 'clean up' the crests/'zeros' for a tolerable ≈ 50% d/c mains-frequency square-wave.

-Thus (again, assuming a mains frequency of 60Hz) the waveform at the collector of Q1 is a 'train' of ≈ 50% d/c, 8.333ms 'positive' pulses...

2)
-
U1 is 'programed' for an interval of slightly greater than 8.333ms (said 'overage' chosen to allow for component aging, thermal 'drift', etc).

-U1 is asynchronously 'reset' by each incoming pulse (via Q2-enforced rapid discharge of C1).

-Where input pulses (i.e. pulses apparent at the collector of Q1) occur prior to expiration of the timing interval, U1's output remains 'high'.

-Should an input pulse arrive 'late' (i.e. post time-out) U1's output will go 'low' pending arrival of subsequent input pulses.

3)
-
U3 is 'programed' for an interval of ≈ 500ms --- Please note that such is non-critical and may vary dependent upon several factors (to be discussed in a subsequent post)...

-A low-level input pulse (width ≥ 25μs {typical}) apparent at Q4's base resistor (R7) will reset U3 (via Q3-enforced rapid-discharge of C2) thus initiating a 'ballasting interval'.

-D6 represents the internal 'control LED' of the opto-triac (p/n S101S05V).

-During 'ballasting', U3's output is 'high' extinguishing D6 (via the circuit including Q5 and Q6) thus 'gating' the triac (not shown) off and opening the mechanical contactor (also not shown).

-The ballast resistor (not shown) no longer bypassed by the contactor is, hence, 'in series with' (i.e. 'ballasting') the main PSU.

4)
-Following time-out of the ballast interval U3's output returns to 'low'

-The triac section being 'gated on' upon illumination of the internal LED (via the circuit including Q5 and Q6) closes the mechanical contactor via completion of electrical connection of its (120V, 100mA ) actuator-coil to the mains.

-Closure of the mechanical contactor bypasses the ballast resistor thus connecting the main PSU directly to the mains.

-Notice: To prevent false switching of the opto-triac, the mechanical contactor's coil must be bypassed by a snubber network! -- A discussion of this issue will be offered for interested readers in a later post....

Please note that I have attached both the schematic file and my model for the LM7809 to this post --- Should you be unable or unwilling to 'eff around' with adding the model to your Spice installation, you may, of course, replace the subcircuit-PSU with a 9V DC 'voltage source' that said, power-fail analysis requires retention of C5...

Please know that I intend to post several simulation 'screenshots' of various points/conditions as soon as time permits (sometime this week)...

And - Because many refuse to open 'attachments' -- Below is the 'copy and paste-able' text of the LM7809 model (Aluminium hats available upon request;)):

////// Begin LM7809 Netlist//////

.SUBCKT LM7809 Input Output Ground

*
*(Note by 'Hypatia's Protege') -- This is my 'quick and dirty' dedicated LM7809 adapted from a generalized LM78XX model exhibited/authored? by Yuri Belenky...
*
*
*Note that the following are 'hard wired' (i.e. coded as 'immediates') consistent with a fixed Vout ~ 9V.
*
*Gain*Feedback product ('AV_Gain') := 924.15.
*Quiescent current adjustment resistance ('R1') := 1836 Ohms.


* Note: This model will allow some current flow to 'Node 0' - such
* is not part of the actual EMF regulator circuit.
*
* Band-gap EMF source:
*
* The source is off when Vin<3V and fully on when Vin>3.7V.
* Line regulation and ripple rejection) are set with
* Rreg= 0.5 * dVin/dVbg. The temperature dependence of this
* circuit is a quadratic fit to the following points:
*
* T Vbg(T)/Vbg(nom)
* --- ---------------
* 0 .999
* 37.5 1
* 125 .990
*
* The temperature coefficient of Rbg is set to 2 * the band gap
* temperature coefficient. Tnom is assumed to be 27 deg. C and
* Vnom is 3.7V
*
Vbg 100 0 DC 7.4V
Sbg (100,101),(Input,Ground) Sbg1
Rbg 101 0 1 TC=1.612E-5,-2.255E-6
Ebg (102,0),(Input,Ground) 1
Rreg 102 101 7k
..MODEL Sbg1 VSWITCH (Ron=1 Roff=1MEG Von=3.7 Voff=3)
*
* Feedback stage
*
* Diodes D1,D2 limit the excursion of the amplifier
* outputs to being near the rails. Rfb, Cfb Set the
* corner frequency for roll-off of ripple rejection.

*
* The opamp gain is given by: Av = (Fores/Freg) * (Vout/Vbg)
* where Fores = output impedance corner frequency
* with Cl=0 (typical value about 1MHz)
* Freg = corner frequency in ripple rejection
* (typical value about 600 Hz)
* Vout = regulator output EMF
* Vbg = bandgap EMF (3.7V)
*
* Note: Av is constant for all output EMFs, but the
* feedback factor changes (hence the AV_Feedback product's role in determination of Vout).
*
Rfb 9 8 1MEG
Cfb 8 Ground 265PF
Eopamp 105 0 VALUE={2250*v(101,0)+924.15*v(Ground,8)}
Vgainf 200 0 {924.15}
Rgainf 200 0 1
*Eopamp 105 0 POLY(3),(101,0),(Ground,8),(200,0) 0 2250 0 0 0 0 0 0 1
Ro 105 106 1k
D1 106 108 Dlim
D2 107 106 Dlim
..MODEL Dlim D (Vj=0.7)
Vl1 102 108 DC 1
Vl2 107 0 DC 1
*
* Quiescent current modelling
*
* Quiescent current is set by Gq, which draws a current
* proportional to the EMF drop across the regulator and
* R1 (temperature coefficient .1%/deg C). R1 must change
* with output EMF as follows: R1 = R1(5v) * Vout/5v.
*
Gq (Input,Ground),(Input,9) 2.0E-5
R1 9 Ground {1836} TC=0.001
*
* Output Stage
*
* Rout is used to set both the low frequency output impedence
* and the load regulation.
*
Q1 Input 5 6 Npn1
Q2 Input 6 7 Npn1 10
..MODEL Npn1 NPN (Bf=50 Is=1E-14)
* Efb Input 4 VALUE={v(Input,Ground)+v(0,106)}
Efb Input 4 POLY(2),(Input,Ground),(0,106) 0 1 1
Rb 4 5 1k TC=0.003
Re 6 7 2k
Rsc 7 9 0.275 TC=1.136E-3,-7.806E-6
Rout 9 Output 0.008
*
* Current Limit
*
Rbcl 7 55 290
Qcl 5 55 9 Npn1
Rcldz 56 55 10k
Dz1 56 Input Dz
..MODEL Dz D (Is=0.05p Rs=3 Bv=7.11 Ibv=0.05u)
..ENDS
*$

////// End Netlist //////


Very best regards
HP:cool:

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