As a hobbiest (NON engineer), I am designing a small signal amp in the most proper way I know how through my methods of calculations, and imperical breadboarding and measurements and tests, using a calculator breadboard and components, oscilloscope, audio signal generator,

resistor sub box. and multimeters. My method is design and build and test and make adjustments as necessary, and recalculate build and test until it works according to the constraints I put for it.

This will be added to as I progress in this project...

arbitrary chosen = #

F = 400 HZ #

Vout pk = 4V. #

Av. = 4000 #

Vin pk. = 1mV. #

Zin > 10K #

VCC = 12V. = (3 x Vout pk) #

-------------------------------------------------------

Stage Q1:

VC = 6V.

ICmax pk = 100 mA. #

Vout pk = 4V. #

VC- pk-pk = 2V.-10V.

ICmin = VC of 10V. so 2V. dropped across RC = VRCmin

ICmax = VC of 2V. so 10V is dropped across RC = VRCmax. @ ICmax of 100mA.

Rout = RC1 // RL = { ( VRCmax / ICmax.)} = { (10V. / 100mA.)} = 100 ohms.

RC1 = RL = (2 x Rout) = 200 ohms.

ICQ1 = ( VC / RC) = (6 / 200) = 30mA.

RC1 = 200

Av. 10 #

RE1 = (Rout / Av.) = 10

VRE1 = 0.3V

VRB1 = 1V

RB1 = 180 #

IB1 = 5.5mA

RB2 = 1.8K

Vinsig. = ( Vout pk. / Av. ) = (4 / 10) = 0.4Vin pk.

static measure:

VC1 = 5.7V.

VB1 = 1.07V.

Dynamic test:

NO load = Vinsig pk. 400mV (distortion on the positive pk.) flat @ 350mV.pos. pk.

NO load = Vinsig pk. 200mV. (NO distortion)

Conclusion : No load causes a change in the INPUT waveform:

Lower Vinsig. removes distortion, normal waveform.

Raise Vinsig. to designed value 400mV. with No load and check VRE1,

VRE1 = 0.33V. NO load

VRE1 = 0.35V. 200 ohm load.

IRE1 = 33mA - 35mA.

delta IRE1 = 2mA.

Shows that With the small value of RE1 of 10 ohms causes more IB to flow under heavy

Vsigin, thereby shunting the signal. When I replace the 200 ohm load, then Vinsig. has proper waveform, no distortion, @400mV pk. but Vout pk, shows around 3.5V pk.

Res. sub box, shows 300 ohms Load, gives me design values of 400mV pk. Vin,

with Vout pk. of 4 volts NO distortion.

Assuming a low Beta, of 50, would make RE1 be around 500 ohms to the signal, so it is the divider resistors that needs to be raised to get a higher Zin.

So to get 4V. pk. out @ 200 ohm load which is my constraints I will rework the divider resistors, for a higher values.

to be continued:

This is very interesting, if I raise RB1 the waveform gets worst, but if I lower it from 180 to 164 ohms, then VC is at 6.03V. the input waveform is almost no distortion, but doesn't quite reach 400mV, pk on the pos half, but reaches it on the neg side.

YThis is going to be a project in learning how to design the input impedance of a basic amp, load value as well as all the other components contribute to the signal input waveform, as the transistor conducts less the signal input has less distortion, but the amplitude goes down, as the transistor conducts more beyond certain value the signal input goes down in amplitude while remaining NO distortion.

This is a whole new learning experiance in amp design, just getting the proper values needed to keep the integrity of the input signal.

To be continued:

Alright Now I'm getting somewhere,

First I disconnected the generator from the amp stage and set my generator with my oscilloscope to read 400mV pk.

Then hooked it up to the input of the amp stage and the waveform dropped to exactly 100mV. pk. (input signal)

Now I disconected the emitter resistor first and seen no big change in recovering the input amplitude, put back the emitter RE1 resistor, and disconnected the divider resistors, RB1 and RB2, and the signal amplitude was restored, with no distortion.

WHY THE DISTORTION?

Now for all the distortion I was getting before, was because of the stupidity, of raising the input voltage with the signal connected to the amp. That's a NO NO....because when I disconnected the amp stage my waveform reading on the oscilloscope, went way off scale, telling me whoops, can't adjust the input signal when it is coupled to the stage, No wonder it was so distorted I was driving the amp with a couple of volts signal instead of mV...

Alright that's figured out.

With 160 ohms for RB1 and the 1.8K for RB2 gives a nice VC of 6.03V.

Good bias there, but input waveform due to low Zin of divider drops the input amplitude to 100mV. pk.

So I do need to increase the divider impedance, while trying to keep the Av. as close to design values as possible, if I increase the divider impedance too far I then risk base current loading, which makes the divider voltage dependant on the transistor base current rather than the divider current itself. Again Not too good...

To be continued:

Now something else I need to consider, is that my signal generator has an Zout of around 700 ohms, so I'm trying to design this stage, which requires a lower Zin at this point and trying to use my generator with higher Zout, is going to of course cause discrepancies, so I'll have to maybe use the -20 and -40 db attenuator and see what I can do.

If that doesn't work than the best way to approach this is to just go by whatever attenuation is happening and just keep the signal waveform out of distortion, and check Voutput to make sure I'm getting the Av. that i want with no distortion.

Maybe that's what I need to do...

To be Cont.:

RB1 now = 270 ohms

RB2 now = 3K

RE1 remains at 10 ohms

RC1 = Rload remains at 200 ohms

static test:

VC = 6.14V.

VRB1 = 0.99V.

Ok with these new values for the divider resistors everything is working good, I randomely put 3 different transistors in this stage and every one gave the same input and output waveform NO distortion and the same Av.

However I will have to adjust the Av. for this stage because input signal shows 120mV. pk. and Vout is 1V. pk. Av. = 8.33

Since I don't have a whole variety of caps, to choose from to get the extra AC gain. So I'll kepp this stage at Av. of 8.

to be cont:

Calculate Zin of this stage:

Assume beta = 50 - 100 (for doing Zin calculations)

Rdiv = 247 ohms

{(RB1 // RB2) // B x RE1} approx. = (166 ohms. - 198 ohms)

Alright that's just to low, or else I'll be cascading stages all day trying to get the Av. I need.

So I will rework the values to get double than what this is right now.

with Beta chosen to be 50 :

I want Zin to be from 330 - 400 ohms

RB1 x RB2 / (RB1 + RB2) = Rdiv.

and { (Rdiv. x 500) / (Rdiv + 500)} = Zin = to {(RB1 // RB2) // B x RE1}

So { - (B x RE1 x Zin) / ( Zin - (B x RE1) } = Rdiv.

B = 50, Zin = 330

{- 500 x 330) / (330 - 500) = 970 = Rdiv. = RB1 // RB2

so 970 = (RB1 // RB2) = Rdiv.

Therefore I'll choose 1K ohms for RB1.

RB2 = { (Rdiv. x RB1) / (RB1 - Rdiv.) }

RB2 = 32.3K ohms.

Now quick voltage check calculation:

(12V. x 1K) / (1K + 32.3K) = 0.36V. Not feasable, I need 1V.

So I'll solve for RB2 using ohms law.

RB2 = 11K

I'll change these values and see if any significant change in base current loading.

RB1 = 1K

RB2 = 11K

static test:

need to make RB1, = 1.2K

VC =5.90V.

VRB1 = 1.02V.

Dynamic tests:

Shows good results as before.

Same VC and waveform input and output, with 3 different transistors.

Calculate Zin of this stage now:

Rdiv = 1081

Zin = 342 - 519 where beta is 50 -100 for calculations.

I like those Zin values.

To be cont.: