small signal amp exp. page 3

PAGE 3 REDESIGN working from input to output stage.

At this point I'm running into clipping problems when I add a fourth stage,
I check the DC bias for each stage and the VC. is around the 1/2 VCC area.

I check the Av. each individually, and I get the gains required, but coupling them is when I run into problems,
with clipping of the waveform.

So I will start over again:

This time I need to check the audio frequency generator, Volt output, because when I get in the very low millivolt region
I run into problems with signal oscilating and rf noise. Showing on my scope.

Audio generator = 10mV. pk. @ Zout = 700 ohms is the minimum where there is good clarity of the waveform on the scope.

So I will use that as my baseline Vin. for my amp design.

Now since my Vin, is established I will design from the input to the output stage, that way I can design each stage Zin,
with the proper Vb, needed to handle the signal each stage recieves, because I think what was happening was that the signal
was overdriving the stages. so I will use the input voltage to determine as much as possible, what value of Vb I need for each stage.

Vin. pk. = 10mV.
Vout. pk. = 4V.
Rload = 200 ohms.
VCC = 12V.

Alright Now I'm getting somewhere with this,
I hace been running into problems with overdriving the stages, and impedances, so when I took all coupling caps out and disconnected the load on the output stage, so now my transisitor stage is just DC analysis only, I measured my VC, and VB, everything looked good, then keeping my voltmeter hooked to VB point, (2.36V)

I coupled the signal generator into this stage, and observed the waveform with negative peaks around 4 volts, but positive flats at around 3 volts. Then I observed on the voltmeter, that VB was reading
- 0.47V, so as I decreased signal input the voltage began to rise to 0V.
and then eventualy back to 2.36V. and the waveform was around 1V pk.
with zero distortion.

I calculated the voltage pk. on my scope to be 700mV pk.
I've read it in all my course books about the input signal driving a transistor stage into saturation, and things, but now I understand this much better, that the signal should have NO affect on the BIAS of the stage it's feeding into, which means signal impedance must be lower than stage impedance, as well as base voltage must be sufficiently higher than pk. voltage of input signal to handle the excursion in a linear way.

My method now will be to design the stages from the input going to the output, trying to keep the voltage VB at each stage to be around 4 times greater than the signal feeding into it. And see if that helps keep the stages from overdriving eachother.

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