Pre notice: the following has some numeric values listed that are to be taken with certain respect as the LT Spice (used to derive those numbers) uses an equitable , say a "P/N-MosFet-s" , to form it's quantized OUTPUT , the performance of these counter types is much dependent on actual hardware/technology used -- so basically the chapter is much about nothing , i only needed a reliable D-flop for a bit more sophisticated virtual "Digital" implementation of such
The variety :
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PS! _n_o_n_e_ (no any) of these Flops were tested this time at slow changing inputs - it's because they are idealized and won't perform much differently - but the realistic ones may start to strobe and function unpredictably at such !!!
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Update 2018-12-31 23:12 UTC :: Apx. LTSpice definitions used for above logic gates ::
Value2 = >>
BUF Vhigh=5 Vlow=0 td=5n
SCHMITT Vhigh=5 Vlow=0 td=6n vt=2.1 vh=.44 (apx. 74HC14 . . . most likely . . .)
- - - - - - - - - - - - - - - - - - - - - - - - ! , 3/7 , (3/17)/2 -- of the Vhigh
NAND Vhigh=5 Vlow=0 td=7n
NOR Vhigh=5 Vlow=0 td=11n
SR3G Vhigh=5 Vlow=0 td=13n
XzOR Vhigh=5 Vlow=0 td=23n
DFLP Vhigh=5 Vlow=0 td=41n
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The variety :
The 1-st design i once came up on my own - after studying the function of 7474
the C1 stands for negative going pulse triggered , C0 for positive going 1
the Yellow is non-inverting output K1 -- and the Orange M1
the second is modified master slave D-Flop the CMOS counters and registers use
Red Clock means C0 , means positive going clock triggered change
3-rd : JK-trigger to MOD2 or D-trigger -- it's about how you configure it
doubling the gate control before the OUTPUT_RS-Trigger reduces occasional instabilities
The 4-th -- the 7474
Finally something i call a pulse counter (a modified Pulse RS-Trigger)
amazingly -- turns out to be the winner of this little contest . . .
. . . with more realistic Digital Logic Gates the best performing competitors tend to be JK-Flop and 7474
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¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
PS! _n_o_n_e_ (no any) of these Flops were tested this time at slow changing inputs - it's because they are idealized and won't perform much differently - but the realistic ones may start to strobe and function unpredictably at such !!!
______________________________________________
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
Update 2018-12-31 23:12 UTC :: Apx. LTSpice definitions used for above logic gates ::
Value2 = >>
BUF Vhigh=5 Vlow=0 td=5n
SCHMITT Vhigh=5 Vlow=0 td=6n vt=2.1 vh=.44 (apx. 74HC14 . . . most likely . . .)
- - - - - - - - - - - - - - - - - - - - - - - - ! , 3/7 , (3/17)/2 -- of the Vhigh
NAND Vhigh=5 Vlow=0 td=7n
NOR Vhigh=5 Vlow=0 td=11n
SR3G Vhigh=5 Vlow=0 td=13n
XzOR Vhigh=5 Vlow=0 td=23n
DFLP Vhigh=5 Vlow=0 td=41n
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[End of this Post]