Set 1

Here's the first set, chaps.

Please read the introduction post.


For the figure shown in figure 1.10, with Vin=30V and R1=R2=10k, find (a) the output voltage with no load attached (the ope-circuit voltage); (b) the output voltage with a 10k load (treat as a voltage divider, with R2 and R1 combined into a single resistor); (c) the Thevenin equivalent circuit; (d) the same as in part b, but using the Thevenin equivalent circuit; (e) the power dissipated in each of the resistors

Show that Rload=Rsource maximises the power in the load for a given source resistance.
Determine the voltage and power ratios for a pair of signals with the following decibel ratios: (a) 3dB, (b) 6dB, (c) 10dB, (d) 20dB.
Derive the formula for the capacitance of two capacitors in series.
Show that the rise time (the time required to go from 10% to 90% of its final value) of this signal is 2.2RC.
R1=R2=10k, and C=0.1μF in the circuit shown in Figure 1.34. Find V(t) and sketch it.

A current of 1mA charges a 1μF capacitor. How long does it take the ramp to reach 10 volts?
Use the preceding rules for the impedance of devices in parallel and in series to derive the formulas (Section 1.12) for the capacitance of two capacitors (a) in parallel and (b) in series.

Show that if A=BC, then A=BC, where A, B and C are magnitudes.
Prove that a circuit whose current is 90° out of phase with the driving voltage consumes no power, averaged over an entire cycle.
Show that all the average power delivered to the preceding circuit winds up in the resistor. Do this by computing the value of VR2/R. What is that power, in watts, for a series circuit of 1μF capacitor and a 1.0k resistor placed across the 110 volt (rms), 60 Hz power line?

Show that adding a series capacitor of value C=1/ω2L makes the power factor equal 1.0 in a series RL circuit. Now do the same thing, but with the word "series" changed to "parallel."

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