This tutorial introduces and explains the fundamentals of how flip-flops work.

There are four basic types of flip-flops as follows:

Firstly, let us review basic logic functions and gates:

U1, U2 and U3 show the logic symbols for three basic logic functions, OR, AND and NOT, respectively.

U1B, U2B and U3B show alternative forms of the same functions derived from their DeMorgan's equivalent.

U4, U5 and U6 show three other symbols and their DeMorgan's equivalent.

Here is a simple flip-flop that has a peculiar property that once set, it cannot be reset.

We assume that the circuit starts up with the output at logic-LOW.

The input is LOW with R1 pull-down resistor to GND.

When push-button S1 is pressed, the output of the OR-gate goes HIGH. This presents a positive feedback to the second input. Thus the output of the OR-gate remains high even when S1 is released.

In order to reset this latch, we must be able to break the positive feedback. We can do this by inserting a logic "gate" in the feedback loop.

With S2 in normally-closed position, the AND-gate allows the feedback signal as in the previous circuit. When we press S2, the input to the AND-gate is LOW with R2 pull-down resistor. This forces the output of the AND-gate to LOW and the feedback is broken.

Without realizing it, we have created a Set-Reset flip-flop.

Without changing the functionality of this circuit we will perform some "bubble magic" by utilizing the DeMorgan's equivalent.

Follow along how we morph the previous schematic into the following schematics:

In the above schematic, we are allowed to add two bubbles without altering the logic function of the circuit.

Next, we apply DeMorgan's equivalent to convert the OR-gate to an AND-gate.

We replace the bubble on the input with a NOT gate.

Remember, so far we have not altered the functionality of the circuit.

You will notice that S1 is normally-open while S2 is normally-closed, i.e. a logic-HIGH input from S1 sets the flip-flop while a logic-LOW from R2 pull-down performs a reset.

Let us invert the functionality of S2 by changing S2 to a normally-open push-button.

And with one final twist, we redraw the above circuit and add labels to replace S1 and S2.

There you have it, your basic S-R flip-flop. Some people call this an R-S flip-flop. Same difference.

The interesting thing about this circuit is that it is easy to implement with one logic IC, a quad 2-input NAND gate such as 74LS00 or CD4011.

Now we move on to a clocked flip-flop. Making use of the 2-input NAND gates, we create a CLOCK input as follows:

When CLOCK input is LOW, both U3 and U4 outputs are HIGH, independent of the SET and RESET inputs.

When CLOCK is HIGH, SET and RESET signals are allowed to propagate through the gates as in the previous R-S flip-flop.

Let us represent the behaviour of the flip-flop in the form of a truth table:

RESET|SET|Q output

0|0|no change

0|1|1

1|0|0

1|1|?

As with the unclocked R-S flip-flop, a peculiar thing happens when both SET and RESET are HIGH. Both U1 and U2 outputs are high while CLOCK is HIGH. More importantly, what happens when the CLOCK input returns to LOW while both SET and RESET inputs are HIGH?

Let us remove the uncertainty of the above R-S flip-flop by ensuring that SET and RESET cannot both be HIGH at the same time. We eliminate the RESET signal and replace it with SET inverted.

Hence when SET is HIGH, our "RESET" is LOW. When SET is LOW, "RESET" is HIGH.

What we have created here is a D-type or DATA-type flip-flop. All we need to do is replace the label "SET" with "D".

(more to come)

There are four basic types of flip-flops as follows:

- R-S flip-flop
- D-type flip-flop
- T-type flip-flop
- J-K flip-flop

**Basic Logic Gates**Firstly, let us review basic logic functions and gates:

U1, U2 and U3 show the logic symbols for three basic logic functions, OR, AND and NOT, respectively.

U1B, U2B and U3B show alternative forms of the same functions derived from their DeMorgan's equivalent.

U4, U5 and U6 show three other symbols and their DeMorgan's equivalent.

**The Non-Resetable Latch**Here is a simple flip-flop that has a peculiar property that once set, it cannot be reset.

We assume that the circuit starts up with the output at logic-LOW.

The input is LOW with R1 pull-down resistor to GND.

When push-button S1 is pressed, the output of the OR-gate goes HIGH. This presents a positive feedback to the second input. Thus the output of the OR-gate remains high even when S1 is released.

**The Resetable Latch**In order to reset this latch, we must be able to break the positive feedback. We can do this by inserting a logic "gate" in the feedback loop.

With S2 in normally-closed position, the AND-gate allows the feedback signal as in the previous circuit. When we press S2, the input to the AND-gate is LOW with R2 pull-down resistor. This forces the output of the AND-gate to LOW and the feedback is broken.

**Set-Reset Flip-Flop**Without realizing it, we have created a Set-Reset flip-flop.

Without changing the functionality of this circuit we will perform some "bubble magic" by utilizing the DeMorgan's equivalent.

Follow along how we morph the previous schematic into the following schematics:

In the above schematic, we are allowed to add two bubbles without altering the logic function of the circuit.

Next, we apply DeMorgan's equivalent to convert the OR-gate to an AND-gate.

We replace the bubble on the input with a NOT gate.

Remember, so far we have not altered the functionality of the circuit.

You will notice that S1 is normally-open while S2 is normally-closed, i.e. a logic-HIGH input from S1 sets the flip-flop while a logic-LOW from R2 pull-down performs a reset.

Let us invert the functionality of S2 by changing S2 to a normally-open push-button.

And with one final twist, we redraw the above circuit and add labels to replace S1 and S2.

There you have it, your basic S-R flip-flop. Some people call this an R-S flip-flop. Same difference.

**Exercise:**What are the output logic levels when both SET and RESET are HIGH?The interesting thing about this circuit is that it is easy to implement with one logic IC, a quad 2-input NAND gate such as 74LS00 or CD4011.

**Clocked R-S Flip-Flop**Now we move on to a clocked flip-flop. Making use of the 2-input NAND gates, we create a CLOCK input as follows:

When CLOCK input is LOW, both U3 and U4 outputs are HIGH, independent of the SET and RESET inputs.

When CLOCK is HIGH, SET and RESET signals are allowed to propagate through the gates as in the previous R-S flip-flop.

Let us represent the behaviour of the flip-flop in the form of a truth table:

RESET|SET|Q output

0|0|no change

0|1|1

1|0|0

1|1|?

**Exercise:**As with the unclocked R-S flip-flop, a peculiar thing happens when both SET and RESET are HIGH. Both U1 and U2 outputs are high while CLOCK is HIGH. More importantly, what happens when the CLOCK input returns to LOW while both SET and RESET inputs are HIGH?

**Hint:**Think about propagation delays of each gate.**D-Type Flip-Flop**Let us remove the uncertainty of the above R-S flip-flop by ensuring that SET and RESET cannot both be HIGH at the same time. We eliminate the RESET signal and replace it with SET inverted.

Hence when SET is HIGH, our "RESET" is LOW. When SET is LOW, "RESET" is HIGH.

What we have created here is a D-type or DATA-type flip-flop. All we need to do is replace the label "SET" with "D".

(more to come)