Hello.
I ve been trying to sythesize a design of my circuit in xilinx ise. i coded the design in verilog.
The simulations work fine. The problem is this-
When I look at the gate count using the BELS feature in the map report..the number of gates are different frm what i got on manually counting them.
why is this so? Im guessing it has something to do with the LUTs.
But i didn't use any behavioral logic (ie, no if constructs, switch case, loops) so extra gates could not have been added
i practically almost defined each gate and explicitly defined each function..
so why am i getting this huge difference in the number of gates?
is there any way i can have the equal number of gates in the report as well as in my circuit ?
the rtl schematic also looks a bit weird..i didnt even use some of the gates (like there was a 3 input AND in the report but for which there was no mention or need of in my code).. someone help me out please.
I ve been trying to sythesize a design of my circuit in xilinx ise. i coded the design in verilog.
The simulations work fine. The problem is this-
When I look at the gate count using the BELS feature in the map report..the number of gates are different frm what i got on manually counting them.
why is this so? Im guessing it has something to do with the LUTs.
But i didn't use any behavioral logic (ie, no if constructs, switch case, loops) so extra gates could not have been added
i practically almost defined each gate and explicitly defined each function..
so why am i getting this huge difference in the number of gates?
is there any way i can have the equal number of gates in the report as well as in my circuit ?
the rtl schematic also looks a bit weird..i didnt even use some of the gates (like there was a 3 input AND in the report but for which there was no mention or need of in my code).. someone help me out please.