Hello
Just made a simple program with VHDL, Synthesizing and translation was ok, no warnings/errors, But 'fit' gave me warnings (seen at the bottom of this message).
There is one odd thing, it seems that the program is using all of the capacity of this chip, but "fit report" tells that the usage of this chip is hardly over 30%. What is wrong in here? If necessary, i can send the whole report and the source code.
Should i take those warnings seriously, it seems to 'fit' into chip, but i would clear these warnings out.
Tool is Xilinx ISE 7.1i
TechSpec
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
88 /256 ( 34%) 218 /896 ( 24%) 167 /640 ( 26%) 84 /256 ( 33%) 16 /173 ( 9%)
************************** Errors and Warnings ***************************
WARNING:Cpld:265 - Logic for net 'counter_2<12>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
WARNING:Cpld:265 - Logic for net 'counter_2<13>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
WARNING:Cpld:265 - Logic for net 'counter_2<14>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
WARNING:Cpld:265 - Logic for net 'counter_2<15>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
************************* Summary of Mapped Logic ************************
Just made a simple program with VHDL, Synthesizing and translation was ok, no warnings/errors, But 'fit' gave me warnings (seen at the bottom of this message).
There is one odd thing, it seems that the program is using all of the capacity of this chip, but "fit report" tells that the usage of this chip is hardly over 30%. What is wrong in here? If necessary, i can send the whole report and the source code.
Should i take those warnings seriously, it seems to 'fit' into chip, but i would clear these warnings out.
Tool is Xilinx ISE 7.1i
TechSpec
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
88 /256 ( 34%) 218 /896 ( 24%) 167 /640 ( 26%) 84 /256 ( 33%) 16 /173 ( 9%)
************************** Errors and Warnings ***************************
WARNING:Cpld:265 - Logic for net 'counter_2<12>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
WARNING:Cpld:265 - Logic for net 'counter_2<13>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
WARNING:Cpld:265 - Logic for net 'counter_2<14>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
WARNING:Cpld:265 - Logic for net 'counter_2<15>' exceeds physical capacity of device; the logic will be broken into intermediate nodes.
************************* Summary of Mapped Logic ************************
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