Xc2s100

Hi all,
I am using a spartan XC2S100 board and I have written a code in verilog to count from 0-9 and display it on the 7 segement display of the FPGA. The problem is that I have created some counters in between just to introduce some delay so that the transition is visible to eyes but after I program the FPGA nothign happens . I am using Xilinx 6.1 and it does every process perfectly and does not give any warning. Could anyone help me out?? I am including my code..

module counter(leddisp, clk, reset);
input clk,reset;
output [6:0] leddisp;
reg [15:0] count;
reg [7:0] count2;
reg [3:0] count3;
reg [6:0] leddisp;
always @ (posedge clk)
begin
if (reset==1)
count<=15'h0;
else
count<=count+1;
if (count==15'hFFFF)
begin
count2<=count2+1;
count<=8'h0;
end
if (count2==8'hFF)
begin
count3<=count3+1;
count2<=8'h0;
end
end
always @ (count3)
begin
case(count3)
4'h0: leddisp <= 7'b1110111;
4'h1: leddisp <= 7'b0010010;
4'h2: leddisp <= 7'b1011101;
4'h3: leddisp <= 7'b1011011;
4'h4: leddisp <= 7'b0111010;
4'h5: leddisp <= 7'b1101011;
4'h6: leddisp <= 7'b1101111;
4'h7: leddisp <= 7'b1010010;
4'h8: leddisp <= 7'b1111111;
4'h9: leddisp <= 7'b1111011;
default: leddisp <=7'b1111011;
endcase
end
endmodule

Just in case i am inlcuding the constraints file also

NET "leddisp<0>" LOC = "p67";
NET "leddisp<1>" LOC = "p39";
NET "leddisp<2>" LOC = "p62";
NET "leddisp<3>" LOC = "p60";
NET "leddisp<4>" LOC = "p46";
NET "leddisp<5>" LOC = "p57";
NET "leddisp<6>" LOC = "p49";
NET "clk" LOC = "p88";
NET "reset" LOC = "p59";
#NET "switch<0>" LOC = "p50";
#NET "switch<1>" LOC = "p48";
#NET "switch<2>" LOC = "p42";
#NET "switch<3>" LOC = "p47";

Thanks in advance..