I am going through some basic labs using Verilog using the Altera DE2 board with the Cyclone II chip.
I need to make an eight-bit wide 2-to-1 multiplexer.
The information that is given is:
There is a select input s and when s = 0 the mux's output m is equal to input x, and if s = 1 the output is equal to y.
The truth table for the circuit is:
s | m
0 | x
1 | y
It can be described by the following statement:
assign m = (~s & x)|(s & y)
As I mentioned before I have to use this to write a Verilog module that has eight assignment statements like the one above. The circuit has two 8-bit inputs X and Y and produces an 8-bit output, M.
I have to make specific pin assignments so I can download it into the FPGA chip. They are:
-SW 17 will be the input switch s
-SW 0,1,2,3,4,5,6,7 will be the X input
-SW 8,9,10,11,12,13,14,15 will be the Y input
-The SW switches will be connected to the red lights LEDR
-Connect output M to the green lights LEDG 0,1,2,3,4,5,6,7
I think that is all the pertinent information. Below is what I have so far:
I know it's far off, but it's what I got so far. Any help would be appreciated. Even a link to some tutorials on basic Verilog.
I need to make an eight-bit wide 2-to-1 multiplexer.
The information that is given is:
There is a select input s and when s = 0 the mux's output m is equal to input x, and if s = 1 the output is equal to y.
The truth table for the circuit is:
s | m
0 | x
1 | y
It can be described by the following statement:
assign m = (~s & x)|(s & y)
As I mentioned before I have to use this to write a Verilog module that has eight assignment statements like the one above. The circuit has two 8-bit inputs X and Y and produces an 8-bit output, M.
I have to make specific pin assignments so I can download it into the FPGA chip. They are:
-SW 17 will be the input switch s
-SW 0,1,2,3,4,5,6,7 will be the X input
-SW 8,9,10,11,12,13,14,15 will be the Y input
-The SW switches will be connected to the red lights LEDR
-Connect output M to the green lights LEDG 0,1,2,3,4,5,6,7
I think that is all the pertinent information. Below is what I have so far:
Rich (BB code):
module lab01 (m,s,x,y);
input s;
input [7:0] x, y;
output [7:0] m;
assign m = (~s&x)|(s&y)
endmoduleI know it's far off, but it's what I got so far. Any help would be appreciated. Even a link to some tutorials on basic Verilog.
