# worst case transition

Discussion in 'Homework Help' started by anhnha, May 3, 2014.

Apr 19, 2012
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2. ### SneakSZ New Member

Sep 19, 2012
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The nmos transistors' capacitors on their output need to charge up to create an output voltage Y. The time depends on the Rds of the pmos tors and the value of the capacitance of the nmos tors.

Image for (c) ==> all the inputs are low, so all the pos tors conduct, which means that the 3 Rds are in parallel forming a small resistance to charge up the 9C. This will take a small time (with respect to the next case).

If 2 inputs are high and 1 is low then the 9C has to charge through the FULL Rds of the pmos tor which gate was low. This will take a larger time with respect to the previous case. Now you have the worst case time constant = Rds*9*C.

Figure d shows the DIScharge model (falling), the inputs for the nmos are high and the pmos too so the no pmos conducts and the 9C cap isn't connected to Vdd.

Figure e shows the charge model.

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3. ### anhnha Thread Starter Well-Known Member

Apr 19, 2012
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Thank you.
I am trying to calculate rising and falling time for all possible input cases. However, I got stuck with the case below.

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4. ### anhnha Thread Starter Well-Known Member

Apr 19, 2012
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I think the delay will be (R||R)*9C.
However, why the branch R/3 in series with 3C doesn't affect the rising delay?
Is there an intuitive way to understand that?