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http://www.allaboutcircuits.com/worksheets/cmos.html on Sat Aug 11, 2012, Question 23 answer missed one key point about the CMOS transistors shown in the schematic. Not only does the bilateral conduction characteristic solve the problem, but also the intrinsic diode (and for well designed devices, avalanche diode) present between the source and drain of each of the output MOSFETs. This is because the connection of the substrate to the source for the NFET also provides a direct path through its intrinsic D-S diode to VSS for the flyback current present when the relay coil was no longer energized by current through the PFET. This is the case even if power is lost to VDD with the input switch tied to ground. Understanding this feature allows some comfort level regarding circuit failure on loss of power in unknown load conditions.
Worksheets->CMOS logic gates, Q23 answer fine point
- Thread starter RWatkins
- Start date
Thank you for your observation.
Can one quantify this effect? Can we be sure that the intrinsic diodes of the FET will withstand the currents forced trough them?
In any case, it is best that an answer is given within the context that is examined, and in this case, it is the binary state of the gate.
Let's not mess with the minds of the students.
Can one quantify this effect? Can we be sure that the intrinsic diodes of the FET will withstand the currents forced trough them?
In any case, it is best that an answer is given within the context that is examined, and in this case, it is the binary state of the gate.
Let's not mess with the minds of the students.
IRT Georacer,
Indeed I can quantify this, in that the intrinsic diode for a MOSFET as listed in the data sheets, will always be rated for short-term current at a current at least the rating of the MOSFET's long-term current rating. As such, for the worksheet schematic, one can never damage the MOSFET or its intrinsic diode if power is removed. Further, this is likely to become important to any student who might consider energizing a relay or solenoid from a logic-sytle totem-pole MOSFET output, since with only a half-bridge drive (eg. totem pole output to one side of a grounded or VCC inductive device) one cannot get the energy out of the inductor quickly merely by "shutting it off". This can result in delays of many milliseconds to several seconds prior to achieving the de-energized state of the relay or solenoid, and can have disasterous consequences for such a use.
IF one were to design a logic device with a very small well contact, I am sure that my statement could be proven wrong. However, the intrinsic diode is also used for ESD protection on real output transistors, so this would be cutting off one's nose to spite one's face.
Indeed I can quantify this, in that the intrinsic diode for a MOSFET as listed in the data sheets, will always be rated for short-term current at a current at least the rating of the MOSFET's long-term current rating. As such, for the worksheet schematic, one can never damage the MOSFET or its intrinsic diode if power is removed. Further, this is likely to become important to any student who might consider energizing a relay or solenoid from a logic-sytle totem-pole MOSFET output, since with only a half-bridge drive (eg. totem pole output to one side of a grounded or VCC inductive device) one cannot get the energy out of the inductor quickly merely by "shutting it off". This can result in delays of many milliseconds to several seconds prior to achieving the de-energized state of the relay or solenoid, and can have disasterous consequences for such a use.
IF one were to design a logic device with a very small well contact, I am sure that my statement could be proven wrong. However, the intrinsic diode is also used for ESD protection on real output transistors, so this would be cutting off one's nose to spite one's face.
