Errmm... that's inconsistent.It means that current flows out of the output and into the load. A positive current flows into a load. If you want to use the opposite sign convention you can, but you have to be consistent
why it's negative?It means that current flows out of the output and into the load.
I think you will find that all TTL datasheets use this convention. See specs for IOH and IOL.Tell us where are you reading this, so that we can take a look.
No it is not inconsistant at all. It is negative as it leaves the source and changes sign as it goes into the load. If the node is any point on the conductor between the source and the load then KCL is satisfied because the sum of the currents is zero. Try reading what I wrote one more time with feeling.Errmm... that's inconsistent.
The OP wrote:No it is not inconsistant at all. It is negative as it leaves the source and changes sign as it goes into the load. If the node is any point on the conductor between the source and the load then KCL is satisfied because the sum of the currents is zero. Try reading what I wrote one more time with feeling.
You are correct about the adoption of a single convention for early TTL, and maybe RTL and DTL datasheets too, where a source current had a negative sign and a sink current had a positive sign. This convention also carries over to present day CMOS logic which tends to have symmetrical drive unlike TTL outputs which could usually sink way more current than they could source.
Nothing would change however if you chose to adopt the alternate convention.
Your first statement says the load current is negative:what the meaning of this
HIGH Level Output Current = -0.4 mA in OR gate(7432)
Your second statement says the load current is positive:It means that current flows out of the output and into the load.
A positive current flows into a load.
Maybe I am misinterpreting your comments, but I thought your second comment contained a typo.If you want to use the opposite sign convention you can, but you have to be consistent
You're right. I didn't noticed. Never used TTL ICs much.I think you will find that all TTL datasheets use this convention. See specs for IOH and IOL.
The sign change happens in a "node" right on the wire between the source and the load. It just so happens that this "node" has only two branches. The current is negative coming coming out of the HIGH output and into the "node". It changes sign and becomes positive going from the node into the load. Apply KCL to the node and a positive current and a negative current sum to zero and all is right with the world. At least that is the way I'm looking at it. Your mileage may vary.The OP wrote:
Your first statement says the load current is negative:
Your second statement says the load current is positive: Maybe I am misinterpreting your comments, but I thought your second comment contained a typo.
by Aaron Carman
by Jake Hertz
by Jake Hertz
by Aaron Carman