Why does this 7 seg not work?

Thread Starter

arthur92710

Joined Jun 25, 2007
307
Why does this 7 seg not work?


The BCD counter counts right but the 7seg does not light up.

Ok I fixed that, now it count 0-9, but shows odd combinations,

Those odd combinations were the inverted numbers. also it counts down insted of up.
 

SgtWookie

Joined Jul 17, 2007
22,230
Does it count from 0 all the way to 9 and display all of the digits correctly?

Or does it skip around, and show odd displays in the middle? If this is happening, you have some of the connections between U1 and U2 swapped around.

Do you have bypass capacitors across the ground/Vss and Vcc/Vdd pins of both ICs?
 

Thread Starter

arthur92710

Joined Jun 25, 2007
307
Thanks but I figured it out. It was giving me so many problems last night but I came back to it in the morning and got it right.


what happened was I was using a common anode display, I needed a common cathode display. To fix the 9-0 counting U1-U/D had to be high.
 

pfofit

Joined Nov 29, 2006
57
arthur, You can simplify your zero to 59 counter. some ideas
With your circuit as is:
U14,15 and u9 can be eliminated.
using a truth table, B and C of your tens counter will only be both 1 at count 6, therefore A & D are "don't care".

One unused pin of U7 can be pulled to Vcc and the other input can be connected to the output of U8 and then the output of U7 will be your reset pin at a count of 60.

Rethinking , the circuit as a whole can be redesigned to further eliminate it down to just three gates:

Output D of your ones counter falls from 1 to 0 going from count 9 to 0.
Since the 4510 is clocked on the rising edge, an inverted ones counter D signal can become the rising edge clock of your tens counter. No need for the carry pins. Since the tens is clocked by the ones counter, the reset can be obtained by the tens counting from 5 to 6.

So using 3 gates of an 4011 NAND chip:
one gate used as an inverter/NOT( input pins of gate tied together) on the D output of the ones counter to obtain a rising clock pulse for the tens counter CLK.

two gates to make an AND for the B & C of the tens counter as a reset pin for both counters (one as an NAND of B&C and then another in series as an NOT)

cheers
 

Thread Starter

arthur92710

Joined Jun 25, 2007
307
Thanks for that, reducing the number of components would be really helpful, It makes it cheaper, it uses less power, takes up less room and the chances of get in something wrong because of a extra part is lowered. So thanks.

I have upgraded the circuit since the last post. here is the new one.


Its basically the same but 3x bigger. With the next changes I will use your ideas.
 

pfofit

Joined Nov 29, 2006
57
Aha!! the plot thickens, and i thought you were just looking for 60 counter!
Rethinking , the circuit as a whole can be redesigned to further eliminate it down to just three gates:

Output D of your ones counter falls from 1 to 0 going from count 9 to 0.
Since the 4510 is clocked on the rising edge, an inverted ones counter D signal can become the rising edge clock of your tens counter. No need for the carry pins. Since the tens is clocked by the ones counter, the reset can be obtained by the tens counting from 5 to 6.

So using 3 gates of an 4011 NAND chip:
one gate used as an inverter/NOT( input pins of gate tied together) on the D output of the ones counter to obtain a rising clock pulse for the tens counter CLK.cheers
Um, although the theory is fine, I'm not sure why i excluded the use of the carry out on the ones counter. It is a decade counter and that's what it's there for.:rolleyes:
Perhaps it was the inverters and U8 to capture a zero... :(
That's what I get for trying to do something in my (getting old) head.:)

nevertheless, you can use the carry out from the ones into the carry in of the tens counter and eliminate yet another gate.

never stop thinking eh.
 
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