I've found many papers on tree adders like Sklansky, Kogge-Stone etc. The drawings never show how a carry-in that is non-zero is consumed so that it propagates to the other stages. The grey and black cells don't show a carry-in. Does someone have a link that shows a drawing or explanation of where in the 3 stage parallel prefix architecture the carry- in is used besides the calculation of the first sum bit like this:
assign sum[0] = can ^ P[0];
Thank you!

 

Sorry ,
my crystal ball is not functioning at the present :->
( I did not see that coming )

give us some links as to the docs your referring to please, so we can see the grey and black cells you refer to .

 

Thank you for your reply. I’m looking at IEEE publications. If you have access, here are some titles:
Area Efficient Modified Booth Adder based on Sklansky Adder
PERFORMANCE ANALYSIS OF PARALLEL PREFIX ADDER FOR DATAPATH VLSI
A New Low-Power, Low-area, Parallel Prefix Sklansky Adder with Reduced Inter-Stage Connections Complexity
just searching for Sklansky will find many more.

If you don’t have access.. This is a link that has similar information but not as detailed. The drawings are the same. It also shows the grey and black cells.
https://www.ijrte.org/wp-content/uploads/papers/v7i5s4/E10920275S419.pdf

I’ve implemented several adders from the drawings and notice that a carry in of ‘1’will show a failure. Ive formally proved the designs so I know they are correct with carry in of ‘0’.
Thanks in advance

 

There also some good lectures and they all ignore the carry in of ‘1’. Attached. This is one of the detailed presentations.

 

I don't know is easy answer,

What would a carry in of 1 mean ?
this would be adding one to the add would it not ?

also

Each bit is made of A + B + C
where C is the carry in from the previous bit,

So the lowest bit, does that not have a C input also ?

Good luck,