Based on the Jtag stage diagram, before Jtag shifts the bits (Shift-DR) the scan cell needs to capture the bits first (Capture-DR). Where does the bit come from? Is it from some test patterns (which has 0s and 1s) and Jtag loads them via digital pins during the capture-DR stage? How many digital pins (exclude Jtag pins) do we need to capture the bits?

 

Based on the Jtag stage diagram, before Jtag shifts the bits (Shift-DR) the scan cell needs to capture the bits first (Capture-DR). Where does the bit come from? Is it from some test patterns (which has 0s and 1s) and Jtag loads them via digital pins during the capture-DR stage? How many digital pins (exclude Jtag pins) do we need to capture the bits?


View attachment 264454
View attachment 264455

Jtag only uses the 4 or 5 pins

TDI, data into the chip
TDO, data out of the chip
TCK, data clock
TMS, Test mode select
and some times
TRST, Reset,

The basis of JTAG, is thats its a state machine as you have seen,
the TDI is used on each rising edge of TCK , to determine which next state to go to

Thus, if I remember correct
no matter where you are in the state machine,
clocking in a constant stream of '1's , is guaranteed to get one back to "reset"

https://www.xjtag.com/about-jtag/jtag-a-technical-overview/

Now the tools that drive the JTAG,
control the state machine,
so you have two parts of the data to send
one the data you want to use, the other the control bits for the state machines,
these are all sent in the serial stream