I don't understand the function of buffer in LDO. Could anyone explain it?
Why adding buffer will help to improve power supply ripple rejection?

 

I wouldn't take internal block diagrams literally. It might be nothing more than an emitter follower or CSEF to improve gate drive current,
ak

 

Could you explain why we need to boost gate current? I thought gate current is zero because gate is open.
I intended to design the buffer using two NOT gates. How about that buffer?

 

The gate is a capacitor that must be charged up and down to vary the channel reistance. The speed at which this happens directly affects the transient response time fo the regulator.

ak

 

The internal diagrams can make all the difference in understanding how a chip works, but they do use shortcuts (like AK said). Fairly often, I check the input stage of an op-amp to see which way the electrons will be flowing. This helps me get the best performance out of the chip, but I (you) have to deal with the fact that they might use the 2 circle symbol for a constant current generator or a circle labeled, "Vref" instead of showing you the transistors.

In that diagram, the mosfet seems to say that this chip is a negative voltage regulator. Connecting the source of a mosfet to the supply voltage seems backwards if you're working on ripple rejection, but the mosfet makes a good level shifter and probably a massive current gain component. That would suggest that a buffer is needed to drive its gate quickly enough.

 

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I intended to design the buffer using two NOT gates. How about that buffer?

NOT gates? The buffer is an analog amp, NOT gates are digital. You can't normally substitute one for the other.

 

Could you explain why we need to boost gate current? I thought gate current is zero because gate is open.

The gate current is only zero when there are no changes in voltage. The capacitance of the gate needs current to charge and discharge.

 

The gate is a capacitor that must be charged up and down to vary the channel reistance. The speed at which this happens directly affects the transient response time fo the regulator.

That makes sense.

In that diagram, the mosfet seems to say that this chip is a negative voltage regulator.

I don't think so. The mosfet here is a PMOS with S is connected to Vin. Both Vin and Vout are positive. I tried to simulate that.

Connecting the source of a mosfet to the supply voltage seems backwards if you're working on ripple rejection, but the mosfet makes a good level shifter and probably a massive current gain component. That would suggest that a buffer is needed to drive its gate quickly enough.

S should be connected to Vin, there is no option, isn't it?

 

NOT gates? The buffer is an analog amp, NOT gates are digital. You can't normally substitute one for the other.

I don't know why but I tried to use this buffer and it gave better PSRR.

This is the Vin- Vout characteristic:

 

OMG. This NOT gates circuit in analog world will not work as a buffer.
This circuit will work as a buffer only in digital world when we have "clean logic signal" at the input (HIGH/LOW). And in this case output also is HIGH or LOW.

But if the input voltage is out of this "digital" range, the circuit will work as a amplifier with high gain. And in your LDO regulator when you closed the loop, this NOT gates will work in linear region as a amplifier. Also notice that in this linear region both P-MOS and N-MOS will conduct, so we have a small short in our circuit .
Why PSRR is better? I don't know. Maybe because this additional amp increase the loop gain.

 

Hi, Jony.
PSRR better while LDO still maintains a relative constant output voltage, so I think it has to work as an amplifier here.

 

Plot derivative of this transfer characteristic and you will now the gan vs Vin.