I am trying to figure out some basics of digital electronics. We have all seen the squared graph of the clock signal.

I have read multiple articles on the internet and still can't figure out whether the moment of signal value switch (I guess on the graph only approximated as point) is important. It would mean it represents the interval when a circuit gets feeds from the inputs and is expected to propagate the values to the outputs, during the interval and the periods of the stable signal are used for something else?

Or the edges are not important but the periods of the stable signal are and the clock signal could be considered as only one additional circuit input, with high or low voltage set? It would mean the circuit starts e.g. reacting on other inputs when the clock signal is set to 1 and it is expected to get values on the outputs somewhere in that clock cycle - when the clock signal is 1 or 0 right after that?

Only the second option seems logical to me but internet authors regularly write that something is expected to happen on the rising edge, and that a circuit should get its outputs in the interval? That is only a term for saying that signal is set to high now?

If the other option I favour is true look at, for example, a counter register made of a single JK flip flop with its inverted output feeding its J input. It is expected to toggle from 0 to 1 in every cycle. If the circuit should start reacting on its inputs when the clock signal becomes 1, what if the result propagates to the outputs while the clock signal is still 1 and there is enough time to propagate values through the whole circuit once more while the clock signal is still 1 in the same cycle, and toggle the counter once more? I see nothing in the circuit that should stop multiple same-clock-cycle propagations if the circuit is fast enough?

Thank you for spending time on helping me to sort this out.

 

You're partly right. The rising edge of the clock is the signal to accept the input into the IC. With the data, various transistors change states, followed by more transistors, and more transistors, ... until the information is ready for the output. The switching of the transistors takes time, so there is a propagation delay between the rising clock signal and the output being ready. This is why a flip flop only changes state only once on a rising clock signal, the propagation delay protects the input data.

 

LDC3, if I understood well the last statement of yours: "the propagation delay protects the input data" - it means that the data will be propagated through the circuit definitely after the clock cycle has passed? The propagation time is definitely longer than the clock cycle for every electronic circuit?

But isn't the output expected on the end of the clock cycle? If multiple JK flip flops are connected to get a counting register doesn't the second flip-flop expect output of the first one ready after one clock cycle in order to get the effect of a clock with twice longer cycle?

If a circuit data propagation definitely lasts longer than a clock cycle (or the interval when the clock signal is high) how should another circuit feeding from the first circuit's output know when to expect the input data?

 

The propagation delay going through all the circuits must be less than the clock period as you surmised. That is what normally determines the maximum clock frequency the circuit can tolerate. Thus a ripple counter, where the output from one stage directly drives the clock of the next stage, has more propagation delay and has a lower maximum clock speed, then a synchronous counter, where each stage is clocked by the input clock.

Many digital circuits require a minimum clock risetime for proper operation which is usually specified in the data sheet. If the risetime is too long than the circuit can give erroneous results.

 

LDC3, if I understood well the last statement of yours: "the propagation delay protects the input data" - it means that the data will be propagated through the circuit definitely after the clock cycle has passed? The propagation time is definitely longer than the clock cycle for every electronic circuit?

But isn't the output expected on the end of the clock cycle? If multiple JK flip flops are connected to get a counting register doesn't the second flip-flop expect output of the first one ready after one clock cycle in order to get the effect of a clock with twice longer cycle?

If a circuit data propagation definitely lasts longer than a clock cycle (or the interval when the clock signal is high) how should another circuit feeding from the first circuit's output know when to expect the input data?

No, you misunderstand. The rising edge of the clock is the signal to change the internals of the IC. The propagation delay is sometimes much shorter than the clock cycle. See a timing diagram for the flip flop. Also look for a circuit with the internal transistors so you can see that the rising edge is important, not whether the line is high or low.

For this IC, http://www.mouser.com/ds/2/405/schs023d-127282.pdf, the propagation delay is 200 ns. The maximum clock frequency is 10 MHz, which has a period of 100000 ns. The propagation delay is much shorter than the clock. The output is ready at the end of the propagation delay, wherever it occurs during the clock cycle.

 

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For this IC, http://www.mouser.com/ds/2/405/schs023d-127282.pdf, the propagation delay is 200 ns. The maximum clock frequency is 10 MHz, which has a period of 100000 ns. The propagation delay is much shorter than the clock. The output is ready at the end of the propagation delay, wherever it occurs during the clock cycle.

You slipped a few digits. 10MHz has a period of 100ns. Thus the propagation delay is twice the maximum clock rate period. This means that, depending upon the application, the maximum usable clock frequency could be less than 5MHz.

 

I know at least one case where both, the front edge (aka leading, rising or positive) and the back edge (aka trailing, falling or negative) of a clock signal in a circuit have well defined uses.

/Edit to add:

In the same circuit, width of pulses is important too. There you have it: edges and width all could matter.

/Edit.

 

You slipped a few digits. 10MHz has a period of 100ns. Thus the propagation delay is twice the maximum clock rate period. This means that, depending upon the application, the maximum usable clock frequency could be less than 5MHz.

OK I was off by a factor of 1000.

What I should have pointed out was that the same IC could have a 10 MHz clock or a 1 MHz clock. The propagation delay is the same. With the 10 MHz clock, the output is ready just before the next rising edge, but with the 1 MHz clock, the output is ready at 1/5th of the high clock period.

 

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What I should have pointed out was that the same IC could have a 10 MHz clock or a 1 MHz clock. The propagation delay is the same. With the 10 MHz clock, the output is ready just before the next rising edge, but with the 1 MHz clock, the output is ready at 1/5th of the high clock period.

OK, I have a quibble with your math again. You said the circuit has a 200ns delay, so the clock would need to be less than 5MHz to insure that the output is there before the next rising clock edge.

 

Both are types of triggering - edge-triggering and level-triggering and are used relative to which one suits better to the circuit design. There are additional circuits that create short impulses from a rising edge of the clock signal and send it to the main circuit input. That way the main circuit gets a high clock-signal input that last enough to invoke propagation but is short enough (for a magnitude of times shorter) to stop circuit from receiving input signal at the moment the feedback comes from the outputs back to the inputs.

The full explanation is given in a Kaz's great answer to the question:
http://electronics.stackexchange.co...triggering-is-preferred-over-level-triggering