What in theCD4555 datasheet tells me how fast the chip can be switched?

Thread Starter

spinnaker

Joined Oct 29, 2009
7,830
Basically you add up TTLH + TPHL1 + Some "Hold" time + TPHL1 + TTHL + Some "Hold" time

1 / Sum = Fmax. Note pay attention to the values for specific supply voltage.

View attachment 164924


This might help http://www.wright.edu/~tdoom/courses/CEG360/review/Timing_Tutorial.pdf

Regards, Dana.

So how do you determine hold time? Read it in the tutorial but not sure I understand.

In this instance would the fastest I can switch this be:

Assuming room temps.

270 + 440 + Hold time + 270 + 440 + hold time or something greater than 1.42u seconds depending on what "hold time" is set to?

If that is the case, that does not seem very fast are there faster decoders?
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,830
Did you try compare with 74HC139 or 40H139. I think they should be faster.
Will check it out.

But am I right? It is some where upwards of 1.42us to switch that chip?

I might actually consider just using Charlieplexing if I can figure out how to switch MOSFETS. I think I know.
 

OBW0549

Joined Mar 2, 2015
3,566
What happens if I operate the chip at 3.3V? What does that do to the switching?
The lower the supply voltage, the slower the switching. At 3.3V, you could probably use a stopwatch to measure the switching speed.

Seriously, 4000-series CMOS is extremely slow. I haven't used it in anything since the late 1970's, and have stuck to 74HCxxx or 74ACxxx chips since then. For instance, a 74HC139 will switch in about a dozen nanoseconds or so (compared to several hundred for the CD4555), and a 74AC139 in 2.5-3.0 nanoseconds.

But am I right? It is some where upwards of 1.42us to switch that chip?
Sounds about right.
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,830
I have some 74LS155s in stock. Is that upwards of 58ns? Am I doing that right? this table tis a little different?

If that is right that should be plenty fast enough.


upload_2018-12-3_20-20-54.png
 

crutschow

Joined Mar 14, 2008
34,285
270 + 440 + Hold time + 270 + 440 + hold time or something greater than 1.42u seconds depending on what "hold time" is set to?
"Hold time" typically refers to clocked devices, such as flip-flops.
It's the time that the input data has to available before the clock pulse arrives.
It doesn't apply to this decoder, which is not clocked.

I think your calculation is a little conservative.
Since the rise and fall times (transition times) are significantly shorter than the propagation delay, I think it can be safely ignored
The maximum frequency of operation when then be 1 / (2*prop delay) or 1/880ns = 1.13MHz.
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,830
"Hold time" typically refers to clocked devices, such as flip-flops.
It's the time that the input data has to available before the clock pulse arrives.
It doesn't apply to this decoder, which is not clocked.

I think your calculation is a little conservative.
Since the rise and fall times (transition times) are significantly shorter than the propagation delay, I think it can be safely ignored
The maximum frequency of operation when then be 1 / (2*prop delay) or 1/880ns = 1.13MHz.

Still not fast enough I think. ;)
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,830
"Hold time" typically refers to clocked devices, such as flip-flops.
It's the time that the input data has to available before the clock pulse arrives.
It doesn't apply to this decoder, which is not clocked.

I think your calculation is a little conservative.
Since the rise and fall times (transition times) are significantly shorter than the propagation delay, I think it can be safely ignored
The maximum frequency of operation when then be 1 / (2*prop delay) or 1/880ns = 1.13MHz.

What propagation delay would I use for the 74LS155? There area couple there.
 

danadak

Joined Mar 10, 2018
4,057
So how do you determine hold time? Read it in the tutorial but not sure I understand.
If the outputs are being used downstream by logic that is clocking some data
into a memory element, like a F-F, then it has to have the data stable for some
minimum time after the clock event occurs. There is a equivalent time called
setup where data must be stable before clock edge occurs.

So if you are not using any outputs as clocks then hold time can in equation can
be reduced to almost to 0.

Lower supply V means the N & P channel devices cannot be turned on as "hard"
as with full supply V, therefore there is less current available to charge the para-
sitic C internal and external to device. So speed drops.

Regards, Dana.
 
Last edited:

danadak

Joined Mar 10, 2018
4,057
"Hold time" typically refers to clocked devices, such as flip-flops.
It's the time that the input data has to available before the clock pulse arrives.
It doesn't apply to this decoder, which is not clocked.
That's setup time, the time data must be stable before clock edge occurs.

Hold time is time data also must be stable after clock edge has occurred.




Regards, Dana.
 
Last edited:

ebp

Joined Feb 8, 2018
2,332
Have a look at the data for HEF4555 Nexperia. They seem to have reworked the whole 4000 series in newer tech and produced very much faster parts. Propagation delay at 5 V is about 300 ns maximum for the 4555. Because 4000 series can't source or sink much current the delays, which are usually measured at the time when signals pass through the point where the voltage is half of the supply, are more heavily influenced by load capacitance than the higher power CMOS families such as 74C and 74AC.

4000 in DIP is almost gone. TI is about the only company still making them. Beware the Intersil parts - they are MIL type, radiation hardened and will be very expensive - if they even exist anymore.

The 4555 differs from most decoders in that the outputs are active HIGH. Most are active LOW.
 

ebp

Joined Feb 8, 2018
2,332
With the LS155, simply use the "max" column as the worst case. Note that in all cases, the delay time must be measured from the last input signal to change level. With something like a decoder, an "enable" signal is likely to feed into the internal gate chain closer to the output and hence have a somewhat shorter delay spec. If the input slew rate is lower than normal, you should expect slightly longer propagation delay time. LS is capable of sinking considerably more current than it can source, to discharging a capacitive load will be faster than charging one - but against that, a LOW is close to the negative (ground) supply voltage than a HIGH is to the positive rail.

The faster CMOS families have quite symmetric source and sink currents. AC and ACT are generally considerably faster than LS and much lower static power consumption. But you're stuck with surface mount only. AC edge speed is also fast enough that transmission line effects will come into play for shorter paths.
 

Thread Starter

spinnaker

Joined Oct 29, 2009
7,830
Lower supply V means the N & P channel devices cannot be turned on as "hard"
as with full supply V, therefore there is less current available to charge the para-
sitic C internal and external to device. So speed drops.

Regards, Dana.

So what does a lower input voltage do to switching if chip is supplied with 5V?
 

danadak

Joined Mar 10, 2018
4,057
So what does a lower input voltage do to switching if chip is supplied with 5V?
The switching specs are shown at various supply voltages. Graphs as well for
prop delay.

The higher the input overdrive V ( V that exceeds threshold spec) aids Rdson of the MOSFET,
so of course speed for charging parasitic C improves.


Regards, Dana.
 
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