I am using Atmega1280v with 8Mhz clock freq.

I have used divider of 128 for adc. So adc freq = 8mhz/128 = 62.5Khz


1. is it sampling rate of adc i.e I can take 62.5kilosamples per second with second.


2. Lets says its true. Now in my code I am doing other tasks also.
Like take adc sample, send on uart, initaiate other tasks.
Now this loop keeps on happening.

So in 1 sec even if I am sampling at 62.5Khz, I will get less no of samples.
Let say it is 20ksps.


So does that means effective sampling rate of my system now comes out to be 20ksps instaed of 62.5ksps

 

According to Zacherly's theorm the sample rate is zacherly what you say it is.

 

I'm not deeply familiar with AT parts, but your reasoning and arithmetic are sound.

One thing, the A/D clock might not be the sample rate. It might be the clock rate for the converter, and the converter might need more than one clock cycle for a conversion cycle. The data sheet can tell you this.

ak

 

What you calculated : 8mhz/128 = 62.5Khz
Is the frequency of the ADC clock .
The AVR ADC requires 13 ADC clock cycles to aquire a sample so you should get
62500 / 13 = 4.8ksps
I suggest you read the datasheet for further info.

If you are transmitting in on UART with a rate higher than your sampling rate then your effective transfer should be close to the sample rate.
It's abit unclear of what you are asking.
Also keep in mind that the UART and ADC conversions happen in hardware . The
CPU only sends the instructions to the registers.

I suggest you set your adc to 'Freerunning mode' and set it to interrupt upon sample completion.
In other words: Your adc will run always (the cpu doesn't care , it can do other things) , then when your adc aquires a sample it will interrupt the cpu which will command the UART hardware to send that sample (after the command the cpu can do what it wants again until the adc has aquired a new sample) etc etc etc

 

@shagas, you are correct its 4.8ksps.

My query:
Let say I have loop before which I have configure adc as 4.8ksps i.e 208us per sample.

1. Infinite Loop starts
2. take 1 adc sample i.e 208us will be spent here
3. Do other activity for 292us . /* Total is 500us (for combined 2 & 3) */
4. Go to step 2


Now if I consider the total time of loop is 500us. i.e 2000 times loop will execute.

1. Now for overall system specs should I mention that adc sample rate is 2000 samples/sec instead of 4.8ksps because effectively I am taking only 2ksps for adc

 

Overall system specs? Is this a school project?
It depends . You can say :
Sample conversion time: 208uS
Sample processing time : 292uS
Effective Sample transfer(or whatever you are doing with them) : 500uS

 

Except that you do not have to wait while the ADC is running. Some of that processing time can be overlapped with acquiring the next sample.

Bob

 

@shagas, you are correct its 4.8ksps.

My query:
Let say I have loop before which I have configure adc as 4.8ksps i.e 208us per sample.

1. Infinite Loop starts
2. take 1 adc sample i.e 208us will be spent here
3. Do other activity for 292us . /* Total is 500us (for combined 2 & 3) */
4. Go to step 2

The ADC is like a separate, independent chip that happens to be in the same package as the CPU. The main program loop doesn't perform the sample acquisition, the ADC does that on its own. Step 2 would be more like "check ADC register for available sample", and would take some (probably) low number of cycles of the 8MHz clock to check for a flag, then retrieve the sample if it's available.