# VHDL

Joined Oct 28, 2005
1
I'm trying to design a rolling average filter that involves a data generator, a filter and a display (7 segment) some switches and a 50Mhz clock which i need to change it to 1Hz.
Any ideas?

#### beenthere

Joined Apr 20, 2004
15,819
Hi,

You can always divide the 50 mHz down, but, unless there's some requirement to use the higher frequency, it will be cheaper and use less board space to get a cmos oscillator to generate the 1 kHz frequency.

#### Dave

Joined Nov 17, 2003
6,970
The way I usually implement this is to create a counter within a process in VHDL. However, I've never tried generating a 1Hz signal form a 50MHz clock, so don't know how well your device will implement the design.

Rich (BB code):
process(clk)
begin

if counter = "<max_divisor>"
then
counter <= "0000";
else if clk = '1' and clk'event
then
counter <= counter + 1;
end if;
end if;

end process;

process(clk)
begin

if clk = '1' and clk'event
then
if counter = "0000"
then
newCLK <= NOT newCLKp;
end if;
end if;

end process;
You may also need to latch the output depending on your requirements.

This design has worked well for generating different clocking rates for implementing display drivers on FPGAs.

However, beenthere's idea is a worthwhile consideration.