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vhdl/verilog code for interfacing DDR# SDRAM to vertex6 or spartran6 fpga

I

Thread Starter

ideas

Joined Mar 16, 2012
7
hi
can any1 plz help me in writing a vhdl/verilog code for interfacing DDR3 SDRAM to vertex6 or spartran6 fpga.
Thank you.
 
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