Hi Forum, Does VHDL have timescale specification like verilog?if yes what is the syntax for that?
V Thread Starter visu9522 Joined Apr 16, 2014 2 Apr 16, 2014 #1 Hi Forum, Does VHDL have timescale specification like verilog?if yes what is the syntax for that?
T tshuck Joined Oct 18, 2012 3,534 Apr 16, 2014 #2 No, not that I'm aware of. The simulation timescale is set in the simulator. I never understood why Verilog included it...
No, not that I'm aware of. The simulation timescale is set in the simulator. I never understood why Verilog included it...