VHDL Newbie Trying to do a 16-to-1 multiplexer

Discussion in 'Embedded Systems and Microcontrollers' started by mad12, Jan 19, 2009.

  1. mad12

    Thread Starter Member

    Oct 9, 2008
    Hey all,

    I am doing my first course that requires us to know VHDL. I have done programming languages before (C and Java) however I have never done anything like VHDL before. We had two classes of introduction but I am still kinda confused how it works. I keep altering my VHDL file, but I really do not see anything wrong with this. We have 5 basic circuits we need to write code for and simulate and the first one is a 16x1 multiplexer. I am assuming that there will be 4 select bits along with the 16 input bits. This is what the source looks like:

    Code ( (Unknown Language)):
    1. library IEEE;
    2. use IEEE.std_logic_1164.all;
    4. ENTITY multiplexer IS
    6.  PORT(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p: IN  STD_LOGIC;
    7.       Sel:    IN    STD_LOGIC_VECTOR(3 downto 0);
    8.       y:    OUT STD_LOGIC);
    9. END multiplexer;
    11. ARCHITECTURE behavior OF multiplexer IS
    12. BEGIN
    13.     PROCESS(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,Sel)
    14.     BEGIN
    15.         IF (Sel="0000") then y<=a;
    16.         ELSIF(Sel="0001") then y<=b;
    17.         ELSIF(Sel="0010") then y<=c;
    18.         ELSIF(Sel="0011") then y<=d;
    19.         ELSIF(Sel="0100") then y<=e;
    20.         ELSIF(Sel="0101") then y<=f;
    21.         ELSIF(Sel="0110") then y<=g;
    22.         ELSIF(Sel="0111") then y<=h;
    23.         ELSIF(Sel="1000") then y<=i;
    24.         ELSIF(Sel="1001") then y<=j;
    25.         ELSIF(Sel="1010") then y<=k;
    26.         ELSIF(Sel="1011") then y<=l;
    27.         ELSIF(Sel="1100") then y<=m;
    28.         ELSIF(Sel="1101") then y<=n;
    29.         ELSIF(Sel="1110") then y<=o;
    30.         ELSE y<=p;
    31.         END IF;
    32.     END PROCESS;
    33. END behavior;
    We are using the Altera Quartus II 8.1 Web Edition software to do our designs. I compile this succesfully (with 4 warnings however), and then I click the Generate Functional Simulation Netlist button and that works successfully. The problem arises when I try to simulate it using a vector waveform file. I am trying all possible combinations of the 4 select bits to make sure I get the correct output, however when I run the simulation I recieve a warning message saying

    There are 16 of these warnings, going from the a to p that is supposed to be my input pins. I was wondering if anyone could help me and let me know what I need to change so that the simulation will yield the 16 different outputs that I am expecting. Thanks in advance for any help and I hope this makes sense!!
    Last edited: Jan 20, 2009
  2. mad12

    Thread Starter Member

    Oct 9, 2008
    After posting I realized I put this in the wrong section. I am pretty sure this should be in the Embedded Systems and Microcontrollers section. If someone could help me move this to the proper forum, I would be thankful! =]
  3. omerkhan

    New Member

    Jan 24, 2009
    hey u can type the program with out using std_logic_vector also,
    u can go for only 1 sel:in std_logic
    try it
    i have done it and got the result