VHDL for comparator

Thread Starter

Predador

Joined May 22, 2008
7
i ned to make an VHDL of the behavior of this comparator

can enibody help me...

any recommendation of a good program to write and to test VHDL?
 
Last edited:

Dave

Joined Nov 17, 2003
6,970
I've never heard of Active-HDL, but concur with Papabravo's suggestion of Quartus II. Another alternative is ISEPack by Xilinx and test via ModelSim.

Dave
 

Thread Starter

Predador

Joined May 22, 2008
7
i am having an hard time with this work
1st i don't find what kind of comparator i am diling with.
2nd i need to describe the beavior of this comparator in VHDL (i am not familiar with)
3- i need to write an “testbench” in VHDl
it is very hard with 2 classes of VHDL laguage to do it.
can enibody put me in the right way...
i am so:confused:


thank you all for your help
sorry for my bad english...

i found this code seems to be like the one i need
Code Listing 3: Nibble comparator nibble_comparator.vhd
package comp is
component
comparator2 port(a, b, AgtB, AeqB, AltB : IN BIT;a_gt_b, a_eq_b, a_lt_b :
OUT BIT);
end component;
end comp;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use work.comp.all;
entity nibble_comparator is
port(a,b: in bit_vector(3 downto 0); gt, eq, lt: in bit; a_gt_b, a_eq_b,
a_lt_b: out bit);
end nibble_comparator;
architecture structural of nibble_comparator is
signal im: bit_vector(0 to 8);
begin
c0:comparator2 port map(a(0), b(0), gt, eq, lt,im(0), im(1), im(2));
c1:comparator2 port map(a(1), b(1), im(0), im(1), im(2),im(3), im(4),
im(5));
c2:comparator2 port map(a(2), b(2), im(3), im(4), im(5),im(6), im(7),
im(8));
c3:comparator2 port map(a(3), b(3), im(6), im(7), im(8),a_gt_b, a_eq_b,
a_lt_b);
end structural;
complet document
 
Last edited:

aiken

Joined May 23, 2008
3
1.use AND, OR,XOR gate to "draw" the circuit first!! Remember you are now doing digital design.
2. Find from your notes or internet: how to write vhdl code for AND OR XOR gate then you should write your design by vhdl
3. use ISE is better than Atlera one, becuase ISE support Testbench for simulation.
4. If you want to write test bench faster, I will suggest you use Actel tools (because they use GUI interface to input signal and output vhdl code testbench for you
 

Thread Starter

Predador

Joined May 22, 2008
7
thank you all for your patience...

whitch one of the ISE products you recomend, they ar very havy...
ISE Webpack 10.1 2.25 GB
ISE Foundation 10.1 Eval 3.33 GB
EDK 10.1 Eval 1.12 GB
ChipScope Pro 10.1 w/Serial I/O Toolkit License Key Eval 385.8 MB
System Generator AccelDSP Synthesis Tool 10.1 Eval 140.04 MB
PlanAhead Design Analysis Tool 10.1 Eval 525.93 MB
and from actel
 
Last edited:

Papabravo

Joined Feb 24, 2006
14,196
The behavioral description would look something like
Rich (BB code):
BEGIN
 PROCESS (a,b)
 BEGIN
  IF    a<b THEN
         result <= "001";
  ELSIF a=b THEN
         result <= "010";
  ELSIF a>b THEN
         result <= "100";
  ELSE
         result <= "000";
  END IF;
  agb <= result(2);
  aeb <= result(1);
  alb <= result(0);
 END PROCESS;
A behavioral description has some advantages over the structural when you are just getting started.
 
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