I'm unfamiliar with that package, so I can't comment.i am triing Active-HDL 7.2SE to help me for this work
yoiu think is good?
complet documentCode Listing 3: Nibble comparator nibble_comparator.vhd
package comp is
component
comparator2 port(a, b, AgtB, AeqB, AltB : IN BIT;a_gt_b, a_eq_b, a_lt_b :
OUT BIT);
end component;
end comp;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use work.comp.all;
entity nibble_comparator is
port(a,b: in bit_vector(3 downto 0); gt, eq, lt: in bit; a_gt_b, a_eq_b,
a_lt_b: out bit);
end nibble_comparator;
architecture structural of nibble_comparator is
signal im: bit_vector(0 to 8);
begin
c0:comparator2 port map(a(0), b(0), gt, eq, lt,im(0), im(1), im(2));
c1:comparator2 port map(a(1), b(1), im(0), im(1), im(2),im(3), im(4),
im(5));
c2:comparator2 port map(a(2), b(2), im(3), im(4), im(5),im(6), im(7),
im(8));
c3:comparator2 port map(a(3), b(3), im(6), im(7), im(8),a_gt_b, a_eq_b,
a_lt_b);
end structural;
and from actel
BEGIN
PROCESS (a,b)
BEGIN
IF a<b THEN
result <= "001";
ELSIF a=b THEN
result <= "010";
ELSIF a>b THEN
result <= "100";
ELSE
result <= "000";
END IF;
agb <= result(2);
aeb <= result(1);
alb <= result(0);
END PROCESS;
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by Jake Hertz
by Jake Hertz