Hi

i'm new in VHDL and i try to compile this Code. I don't understand the error. First i tried google but there was no success to my problem
Can some one give me a hint? I'm using Quartus II.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity LUTmuxMxN is

    generic(
        
        --Zaehlergrenzen
        min             :        natural := 0;    
        max            :        natural := 255    
    );

    port(
    
        -- Systemclock => 2kHz
        clk            :        in std_logic;
        
        --KEY[0] und KEY[1]
        taste0        :        in std_logic;
        taste1        :        in std_logic;
        
        --Helligkeitswert der ausgegeben wird
        brightness    :        out integer range min to max                 
    );
end entity;


architecture verhalten of LUTmuxMxN is

    signal richtung : integer;    
    signal reset_n, enable_heller, enable_dunkler : std_logic;
    
    begin
    
    -- Erkennen ob der LED heller oder dunkler 
    -- eingestellt werden soll
    
    poti_richtung:    process(taster0, taster1)
    
                    begin
            
                        --    Beide Taster gedrückt Reset
                        if (rising_edge(taster0) and rising_edge(taster1)) then
                            reset_n = '1';
        
                        --    Taster 0 (KEY[0]) gedrückt LED leuchtet heller
                        else if rising_edge(taster0) then
                            richtung <= 1;
                            enable_heller <= '1';
                            
                        --    Taster 1 (KEY[1]) gedrückt LED leuchtet dunkler
                        else if rising_edge(taster1) then
                            richtung <= -1;
                            enable_dunkler <= '1';
                            
                        --    zur Vermeidung von Latches, da der Process asynsron
                        --    läuft
                        else
                            richtung <= 0;
                            enable_heller <= '0';
                            enable_dunkler <= '0';
                        end if;
                        
                end process;
    
    poti:        process(clk)

                    variable counter :    integer range min to max;
    
                        begin
                        
                            --syncroner Update mit Systemtakt
                            if (rising_edge(clk)) then
                            
                                if reset_n = '1' then
                                    counter := 0;
                                                            
                                -- heller
                                else if enable_heller = '1' then
                                    counter := counter + richtung;
                                
                                -- dunkler
                                else if enable_dunkler = '1' then
                                    counter := counter + richtung;
                                
                                end if;
                                
                            end if;
                    
                        brightness <= counter;
                
                end process;
                
end verhalten;

[Error messages from Quartus II]

Info: *******************************************************************
Info: Running Quartus II 32-bit Create Symbol File
    Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Apr 11 16:15:35 2013
    Info: Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Thu Apr 11 16:15:35 2013
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DeltaSigmaTop -c DeltaSigmaTop --generate_symbol=C:/Users/Workstation/Desktop/DSF/DeltaSigma/LUTmuxMxN.vhd
Error (10500): VHDL syntax error at firstOrder_deltasigma_DAC.vhdl(32) near text "signal";  expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at firstOrder_deltasigma_DAC.vhdl(33) near text "signal";  expecting "end", or "(", or an identifier ("signal" is a reserved keyword), or a concurrent statement
Error (10500): VHDL syntax error at firstOrder_deltasigma_DAC.vhdl(50) near text "=";  expecting "(", or "'", or "."
Error: Quartus II 32-bit Create Symbol File was unsuccessful. 3 errors, 0 warnings
    Error: Peak virtual memory: 332 megabytes
    Error: Processing ended: Thu Apr 11 16:15:39 2013
    Error: Elapsed time: 00:00:04
    Error: Total CPU time (on all processors): 00:00:03
    Error: Peak virtual memory: 332 megabytes
    Error: Processing ended: Thu Apr 11 16:15:39 2013
    Error: Elapsed time: 00:00:04
    Error: Total CPU time (on all processors): 00:00:03

 

I don't see anything wrong, but I wonder of Quartus expects the module name after "end entity" I've always included the name, so I don't know if quartus will like what you've done or not.

 

THX for your answser. Actually the error was in a second file. So i didn't read the error message very well :/.