Hello,
I'm trying to create a mips R2000-like architecture in behavioral vhdl.
I've written the code for several parts (the ALU, the FSM, etc) but I am a bit confused how to make them work together.
I understand I have to use structural vhdl in the highest level (say cpu.vhd) and I know how to embed a component into a bigger one but how can I assign the output of a single component to the input of another.
For example I know how to assign the clock signal that exists in the highest level to whichever component needs it, but I don't know how to assign the Instruction Memory output (which obviously is not an input of the high level module) to the Instruction Register unit without the highest level module acting as a dispatcher (reading the IM output and then writing it to the IR).
I hope I've clearly stated by problem/confusion.
Any help is deeply appreciated.
I'm trying to create a mips R2000-like architecture in behavioral vhdl.
I've written the code for several parts (the ALU, the FSM, etc) but I am a bit confused how to make them work together.
I understand I have to use structural vhdl in the highest level (say cpu.vhd) and I know how to embed a component into a bigger one but how can I assign the output of a single component to the input of another.
For example I know how to assign the clock signal that exists in the highest level to whichever component needs it, but I don't know how to assign the Instruction Memory output (which obviously is not an input of the high level module) to the Instruction Register unit without the highest level module acting as a dispatcher (reading the IM output and then writing it to the IR).
I hope I've clearly stated by problem/confusion.
Any help is deeply appreciated.