VHDL code for 4bit magnitude comparator(with cascading. 74'85)

Hello everyone,

I have just started learning vhdl and now I am stuck by the coding of 7485.
I checked my soln and its cascading part seems to be wrong since it not working. Could anyone help me? Thanks a lot.


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entity comparator_ca is
Port ( A,B: in STD_LOGIC_Vector(3 downto 0);
Ca,Cb,Ceq : in STD_LOGIC;--Ca,Cb,Ceq are cascading inputs
Ag,Bg,AeqB : out STD_LOGIC);--Ag stands for A is greater
end comparator_ca;

architecture Behavioral of comparator_ca is
begin
process (A,B,Ca,Cb,Ceq)
variable tag,tbg,teq: std_logic:='0';
begin

if A>B then
tag:='1';
tbg:='0';
teq:='0';

elsif A<B then
tbg:='1';
tag:='0';
teq:='0';
end if;

if tag='0' and tbg='0' then
if Ca='1' and Cb='0' and Ceq='0' then tag:='1'; end if;
if Ca='0' and Cb='1' and Ceq='0' then tbg:='1'; end if;
if Ceq='1' then teq:='1'; end if;
if Ca='1' and Cb='1' and Ceq='0' then tbg:='0';tag:='0';teq:='0';end if;
if Ca='0' and Cb='0' and Ceq='0' then tag:='1'; tbg:='1'; end if;
end if;

Ag<=tag;
Bg<=tbg;
AeqB<=teq;

end process;

end Behavioral;
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