vhdl:can value in a array be overwritten??

Discussion in 'Homework Help' started by amenla, Jul 2, 2008.

  1. amenla

    Thread Starter New Member

    Jul 2, 2008
    hey ppl..need ur help.. m doin dis pjt where i need to overwite a pre defined array.. (m usin xilinx)

    ther is dis one more logic that i was tryin...

    i defined a 10 elemnt array and initialised d first five ones.. then in a loop statement i tried loadin d 6th element at clock edge..not workin though..

    is it possible to do smthin like this..?
    cos well m not gettin d o/p n m not sure if its cs of this or some other thing,,
    pls help.! need to submit it soon :(
    thnks a lot gyus :)
  2. arrie

    New Member

    Jun 27, 2008

    Check your grammar, a lot of people who might read your post, struggle to understand what you are trying to say, and then may ignore your post.
    Try typing every word in full for a start.
    You have a typical sms style of writing, yet that does not really fly with a lot of people these days.
    Also give a bit more detail regarding the platform you are using. (Hardware and software tools, etc.)

  3. Reshma

    Active Member

    Mar 11, 2007
    I am not sure what you are trying to convey. I assume you want to generate a clock pulse using a suitable delay between the High and Low states. Here is what you can do:
    *Instead of an array define a vector initialized at some value
    *Increment its value till it reaches a particular value of delay required
    *Make a state transition at this point

    Here is a sample code:

    Code ( (Unknown Language)):
    2. signal cnt : std_logic_vector(7 downto 0):="00000000";
    3. signal check: std_logic:='0';
    5. begin
    7. process(clk)
    9. begin
    10.             if (clk'event and clk ='1') then
    11.                 cnt <= cnt + '1';
    12.                   if cnt = "00100101" then
    13.                     check <= not check;
    14.                     cnt <= "00000000";
    15.                       end if;
    16.             end if;
    18. end process;