vhdl and VGA generation

Thread Starter

throwitdown

Joined Apr 17, 2004
2
Hi,
I posted this in the projects forum, but it is probably more of a programming issue,......................

Please help,
I am i completely stuck on my project. I know what i want to do, but I am not sure where to begin by coding it.
I am implementing a scoreboard using VHDL. I am using a XS40 board to run my code on. The code will count down like a sports scoreboard, and will show the clock counting down on the monitor using the on board VGA.
I have written code which should count down from 12 minutes (12:00:00) to zero seconds, and now I have to figure out how I intend to show this on the screen.
I have broken the monitor into blocks of pixels, 32 blocks across and 24 blocks down. This makes each block 10 pixels each horizontally and 20 vertically.
i have then designed what each pixel would look like on the screen, using a box which is 4 blocks across (40 pixels) by 8 blocks down (160 pixels)
So, in order to set up my design, I intend to have a counter which will count every 10 pixels horizontally for each block, then count every 4 blocks of 10 pixels for each block, then count across in digits. i similar operation would take place vertically.(values of 20, 8, and 3)
I am sorry about not being able to explain this well, but i can post diagrams which will help explain this.
I then intend to store in ROM, the addresses of each block, and whether it will be white or black, and then project it on to the screen. I know the value I have in each address, but I am unsure as to how to make sure they appear how I want them to using the VGA.
I have no idea as to how I am going to implement my design in code. I am not an experienced programmer in VHDL and I only have another 2 weeks to finsh this project.
Here is the initial code I have written for the counters, but have yet to simlute and synthesise.
Library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity GAMECLOCK is
port (
CLOCK: in STD_LOGIC;
RESET: in STD_LOGIC;
RUN : in STD_LOGIC;
DEC : in STD_LOGIC;
umin: out STD_LOGIC_VECTOR (3 downto 0); -- 10
lmin: out STD_LOGIC_VECTOR (3 downto 0); -- 1
usec: out STD_LOGIC_VECTOR (3 downto 0); -- 10
lsec: out STD_LOGIC_VECTOR (3 downto 0); -- 1
umsec: out STD_LOGIC_VECTOR (3 downto 0); -- 1/10
lmsec: out STD_LOGIC_VECTOR (3 downto 0)); -- 1/100
end GAMECLOCK;
architecture of GAMECLOCK is
SIGNAL dec_umin, dec_lmin, dec_usec, dec_lsec, dec_umsec, dec_lmsec : STD_LOGIC_VECTOR (3 downto 0);
begin

lmsec:process (CLOCK, RESET)
begin
if RESET = '1' then
lmsec <= "0000";
dec_umsec <= '0';
elseif CLOCK'event and CLOCK = '1' then
if lmsec = "0000" then
lmsec <= "1001";
dec_umsec <= '1';
else
lmsec <= lmsec - '1';
dec_umsec <= '0';
end if;
end if;
end process
umsec:process (CLOCK, RESET)
begin
if RESET = '1' then
umsec <= "0000";
dec_lsec <= '0';
elseif CLOCK'event and CLOCK = '1' then
if umsec = "0000" then
umsec <= "1001";
dec_lsec <= '1';
else
umsec <= umsec - '1';
dec_lsec <= '0';
end if;
end if;
end process
lsec:process (CLOCK, RESET)
begin
if RESET = '1' then
lsec <= "0000";
dec_usec <= '0';
elseif CLOCK'event and CLOCK = '1' then
if lsec = "0000" then
lsec <= "1001";
dec_usec <= '1';
else
lsec <= lsec - '1';
dec_usec <= '0';
end if;
end if;
end process
usec:process (CLOCK, RESET)
begin
if RESET = '1' then
usec <= "0000";
dec_lmin <= '0';
elseif CLOCK'event and CLOCK = '1' then
if usec = "0000" then
usec <= "0101";
dec_lmin <= '1';
else
usec <= usec - '1';
dec_lmin <= '0';
end if;
end if;
end process
lmin:process (CLOCK, RESET)
begin
if RESET = '1' then
lmin <= "0010";
dec_umin <= '0';
elseif CLOCK'event and CLOCK = '1' then
if lmin = "0000" then
lmin <= "0010";
dec_umin <= '1';
else
lmin <= lmin - '1';
dec_umin <= '0';
end if;
end if;
end process
umin:process (CLOCK, RESET)
begin
if RESET = '1' then
umin <= "0001";

elseif CLOCK'event and CLOCK = '1' then
if umin = "0000" then
umin <= "0001";
else
umin <= umin - '1';
end if;
end if;
end process
end GAMECLOCK;
If any one could help or requires more information, please let me know,
Cheers,
T
 

Dave

Joined Nov 17, 2003
6,970
I'm afraid my knowledge of this subject is minimal, however having looked at the Student recommendations at our University, it seems that a popular and highly recommended book on this topic is: The Students Guide to VHDL by Peter Ashenden.
 
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