Verilog wire definition and usage

Thread Starter


Joined Aug 16, 2007

I am having a problem understanding the usage of the internal and external signals in the Verilog HDL. For example, in my design there is a module with assigned ports. Let's name one of the output port is assigned as follows:


// wires
output wire myouttestport;

In my constraints file the net myouttestport is assigned to a pin:
NET mytestoutpin LOC=A12 | IOSTANDARD = LVCMOS25 | SLEW = FAST;

I would like to use the 'myportout' output signal for internal use somewhere else in the code and use it externally from the pin A12 as defined in the constraints file.

My question is:
what would be the simplest / best / the most professional way to achieve this goal?

Thanks in advance,