Thanks a lot.

I'm using ModelSim

I have already installed Xilinx on my other computer but I have never tried to use it for any code run and don't really how it works.

Look at your waves and see what's happening. Don't just give up. I got your code to work by modifying the testbench.

Yes, I have also tried to fix it and it looks like I'm somewhat successful.

PG1995, before you try to test any more circuits, you need to find out why verilogger isn't working for perfectly good code. It won't be possible to debug code if your simulator isn't working.

I have only one more code to finish then I will be done so start using a new program at this stage doesn't make much sense. Anyway, thanks for the advice.

I was working on a new code for universal shift register. Please have a look on the code. I don't know but its testbench doesn't work at all and I'm getting all these warnings. Could you please help me? Thank you.

/ 4-bit universal shift register

module universal_shift_register(data_out, MSB_out, LSB_out, data_in, MSB_in, LSB_in, s0, s1, clk, rst);


	input [3:0]data_in; // 3210
	input MSB_in;
	input LSB_in;
	input s0, s1, clk, rst;
	
	wire [3:0]data_in;
	wire MSB_in, LSB_in, s0, s1, clk, rst;

	output [3:0]data_out;
	output MSB_out;
	output LSB_out;
	
	reg [3:0]data_out;
	
	assign MSB_out = data_out[3];
	assign LSB_out = data_out[0];
	
	always @(posedge clk) begin
		if (rst==1) data_out <=0;
		else case({s0,s1})
			0: data_out <= data_out;  //hold
			1: data_out <= {MSB_in, data_out[3:1]}; //right, 01
			2: data_out <= {data_out[2:0], LSB_in}; //left , 10
			3: data_out <= data_in;  //  parallel, 11
			endcase
			end
			
endmodule


module testbench;

	wire [3:0]data_out;
	wire MSB_out;
	wire LSB_out;

	reg [3:0]data_in;
	reg MSB_in, LSB_in, s0, s1, clk, rst;
	
	universal_shift_register uni_reg(data_out, MSB_out, LSB_out, data_in, MSB_in, LSB_in, s0, s1, clk, rst);
	
		always begin
			#5 clk = 0;
			#5 clk = 1;
			#5;
			end
			
			initial begin
                           rst = 1;
                        #7 rst=0;
                        #7 s0=0; s1=0; //hold case
                        #7 s0=0; s1=1; MSB_in=1; //right
                        #7 rst=1;
                        #7 rst=0;
                        #7 s0=1; s0=0; LSB_in=1; //left
                        #7 rst=0;
                        #7 s0=1; s1=1; data_in=3; //parallel
                        #14 $finish;
                        end

endmodule

 

The warnings should give you a good hint to your issue. What do you see when you look at the signals from the warning?

Hint: make sure you always declare your port signals properly.

I have only one more code to finish then I will be done

Done with what?

so start using a new program at this stage doesn't make much sense.

It only doesn't make sense because you have someone else debugging your code for you, namely me. It makes perfect sense to fix your simulation issue because you need to be able to debug your own code.