verilog, verilogger, file with 'v' extension

Thread Starter

PG1995

Joined Apr 15, 2011
832
Hi

It appends bit 7 to bits 6 down to bit 0.
Don't you think that it appends bit 7 to bit 0 down to bit 6. In this binary number, 00000001, red "0" is bit #0 and blue "1" is bit #7. For a ring counter at next clock pulse, it will become 10000000. We can see that bit #7 has been appended to bit #0 after the clock pulse. Please let me know if I have it correct. Thanks.
 
Last edited:

Brownout

Joined Jan 10, 2012
2,390
No, the vector 'count' is declared as [7:0], which is understood that the msb, bit 7 is in the left-most position. So, the vector looks like this:

76543210.

After the rotation, it looks like this:

65432107
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Hi

Mux: I'm getting these errors for line #24 to line #27 for 4x1 Mux. I'm trying to use conditional statements. I have highlighted the code from line #24 to line #27. Could you please help me? I

Rich (BB code):
// 32-bit 4 to 1 Mux

module four_to_one(Y,A,B,C,D,Sel,En);

parameter word_size = 32;

input [(word_size-1):0]A;  //array from "0" to "31"
input [(word_size-1):0]B;
input [(word_size-1):0]C;
input [(word_size-1):0]D;

input [1:0]Sel;

input En;

output [(word_size-1):0]Y;
wire [(word_size-1):0]Y;
reg [(word_size-1):0]mux_in;

assign Y = En? mux_in : 32'bz;

always @(A or B or C or D or Sel) begin
	
	(Sel==0)? mux_in <= A:
	(Sel==1)? mux_in <= B:
	(Sel==2)? mux_in <= C:
	(Sel==0)? mux_in <= D:
	32'bz;
	end

endmodule


//stimulus

module testbench;
 
 parameter word_size = 32;
  reg [(word_size-1):0]A;
  reg [(word_size-1):0]B;
  reg [(word_size-1):0]C;
  reg [(word_size-1):0]D;
  reg [1:0]Sel;
  reg En;
  
  wire [(word_size-1):0]Y;


    four_to_one fourMux(Y,A,B,C,D,Sel,En);
        initial
            begin
                A<=28;
                B<=20;
                C<=9;
                D<=5;
                En<=1;

                    Sel=00;
                #20 Sel=01;
                #20 Sel=10;
                #20 Sel=11;
                #20 $finish;
            end

endmodule



Encoder: The following is the code for a priority encoder but you can see here that the waveform for variable "code" is blank. The code looks fine overall but I can only think of one reason for this error. I believe I need to use something like "break" after each case statement to exit the block. Could you please help me to correct it?

Rich (BB code):
module encoder(code,data);

	input [7:0]data;
	output [2:0]code;
	
	wire [7:0]data;
	reg [2:0]code;
	
	always @(data) begin
		case(data)
		data[7]: code<=7;
		data[6]: code<=6;
		data[5]: code<=5;
		data[4]: code<=4;
		data[3]: code<=3;
		data[2]: code<=2;
		data[1]: code<=1;
		data[0]: code<=0;
                endcase
		end
		
endmodule

// stimulus

module testbench;

	reg [7:0]data;
	wire [2:0]code;
	
	encoder encoder1(code,data);
	
	initial
		begin
			data<=8'b10000010;
		#10	data<=8'b00000101;
		#10	data<=8'b01001000;
		#10	data<=8'b00110000;
		#10	data<=8'b00100000;
		#10	data<=8'b01000000;
		#10	data<=8'b00000011;
		#10 $finish;
		end
endmodule
 

Attachments

Brownout

Joined Jan 10, 2012
2,390
For your first issue, don't use 'sel' in a sequential block. Use a 'case' statement instead. Or for priority encoding, use if/else.

For your second issue, you can't use the bits in a case statement like that. The various cases must resolve to a set of mutually exclusive conditions. For example, you can use an enumerated type (red, blue, green, etc.) then your cases would be

case(color)

red:...
blue:...
green:...
etc
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thank you.

For your first issue, don't use 'sel' in a sequential block. Use a 'case' statement instead. Or for priority encoding, use if/else.
I have already done it using if/else statements. But isn't there any way to use 'sel' within a block?

For your second issue, you can't use the bits in a case statement like that. The various cases must resolve to a set of mutually exclusive conditions. For example, you can use an enumerated type (red, blue, green, etc.) then your cases would be

case(color)

red:...
blue:...
green:...
etc
I don't see any reason why bits can't be used in a case statement like that. I still think that it's not working because I need something similar to "break" after each case statement to get out of the block. Perhaps, if you could rewrite my code with corrections then I might get your points. Thanks.

Regards
PG
 

Brownout

Joined Jan 10, 2012
2,390
I'm not gonna rewrite your code. You have to take my word for it, or else look it up. There's nothing I've written that can't be found in a good Verilog reference.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
I'm not gonna rewrite your code. You have to take my word for it, or else look it up. There's nothing I've written that can't be found in a good Verilog reference.
No problem. I didn't ask you to write a code for me. I had a code and was just requesting to codify whatever you were saying into some lines so that I can figure it out. Suppose you are telling someone that first add "a" to "b" then multiply the sum by "1/c", and then that someone requests you that to kindly write it in another form so that he can understand your point. Obviously, it would be simpler as (1/c)(a+b). Anyway, thanks.

Regards
PG
 

Brownout

Joined Jan 10, 2012
2,390
If you tell me EXACTLY what you're trying to accomplish, I'll try to show you how to do it. When I say tell me, I mean in words, not code.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thank you.

Let's forget that code for a moment because I have working version using else/if statements.

The code below for a 4-bit shift register isn't working. It compiles but the waveforms are totally messed up. I'm not sure if the code is logically correct. So, now I'm telling you exactly what my problem is! :)

Rich (BB code):
// 4-bit Shift Register

module shift_reg(A,E,clk,rst);

	input E, clk, rst;
       output A;
	
	reg A, B, C, D;
	
	always @(posedge clk or posedge rst) begin
			if (rst==1) begin
				A <= 0; B <= 0; C <= 0; D <= 0;
                            end
				
			else begin
				A<=B;
				B<=C;
				C<=D;
				D<=E; 
                            end
		end
		endmodule



// Stimulus

        module testbench;

        reg E, clk, rst;
        wire A;
        reg B, C, D;

        shift_reg shiftReg(A,E,clk,rst);

        always begin
            clk = 0;           
            #3  clk = 1;
            #3;               
        end

        initial
             begin
            rst <= 1;

        #5 rst <= 0; E <= 1;
        #5 E <= 0;
        #5 E <= 1;
        #5 E <= 0;
        #5 $finish;
            end
        endmodule
 

Attachments

Brownout

Joined Jan 10, 2012
2,390
Don't make your reset go active at time zero. Try a little delay. Your register signals are looking for a positive change on reset, but nothing happens after T=0, the same time your registers are being initialized. Also, don't use non-blocking assignments in your testbench initial block. The correct way is to use blocking assignments.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thanks a lot.

I made the changes you suggested but the waveforms are still not correct assuming the code is logically correct. This shows the 4-bit shift register which I tried to codify.

Rich (BB code):
// Shift Register

module shift_reg(A,E,clk,rst);

	input E, clk, rst;
       output A;
	
	reg A, B, C, D;
	
	always @(posedge clk or posedge rst) begin
			if (rst==1) begin
				A <= 0; B <= 0; C <= 0; D <= 0;
                            end
				
			else begin
				A<=B;
				B<=C;
				C<=D;
				D<=E; 
                            end
		end
		endmodule



// Stimulus

        module testbench;

        reg E, clk, rst;
        wire A;
        reg B, C, D;

        shift_reg shiftReg(A,E,clk,rst);

        always begin
            clk = 0;           
            #3  clk = 1;
            #3;               
        end

        initial
             begin
            #3 rst = 1;

        #5 rst = 0; E = 1;
        #5 E = 0;
        #5 E = 1;
        #5 E = 0;
        #5 $finish;
            end
        endmodule
 

Attachments

Brownout

Joined Jan 10, 2012
2,390
Try this:

initial begin
#3 rst = 0;
#5 rst = 1;
#5 rst = 0;

Resets are tricky. Sometimes you need to go through a couple iterations. Aisde from that, I don't yet see anything wrong with you code.
 

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thanks.

Unfortunately, it's still not working as intended but if you find the code logically correct then it's better to leave as it is because I'm little short of time.

The code below is for a up/down counter. I see that it's not a good code and there is a lot of room for improvements but I wanted it to be simple.

Do you find it logically correct?

You can see here that the waveforms aren't correct. Could you please help me to fix it? Thanks.

Rich (BB code):
// 3-bit up/down counter

module up_down_counter(count,data_in,clk,rst,counter_on,count_up,load);

	input [2:0]data_in;
	input clk,rst,counter_on,count_up,load;
	output [2:0]count;
	
	wire [2:0]data_in;
	wire clk,rst,counter_on,count_up,load;
	reg [2:0]count;
	
	always @(posedge clk or posedge rst) begin 
		if (rst==1) count<=3'bz;
		else if (load==1) begin
				count<=data_in;
				if(count_up==1) count<=count+1;
				else count<=count-1;
				end		
		else if(counter_on==1) begin
			if(count_up==1) count=count+1;
			else count=count-1;
			end
                     end
endmodule

// stimulus

module testbench;

	reg [2:0]data_in;
	reg clk,rst,counter_on,count_up,load;
	wire [2:0]count;
	up_down_counter up_down(count,data_in,clk,rst,counter_on,count_up,load);
		
		always begin
			clk = 0;
			#10 clk = 1;
			#10;
			end
	
		initial
			begin
				rst=1;
			#4 rst=0;
			#3 load=1; data_in=3; counter_on=0;
            #8 rst=1; data_in=0;
			#8 rst=0; load=0; counter_on=1;count_up=1; 
             #40 rst=1;
			#8 rst=0; load=0; counter_on=1;count_up=0;
			#40 $finish;
			end
endmodule
Regards
PG
 

Attachments

Brownout

Joined Jan 10, 2012
2,390
First things first. I simulated your shift register, and it workd as expected. See insert.

Your counter will never load the starting value because your structure is incorrect. It should look like this:

else if (load==1)
count<=data_in;
else if(count_up==1) count<=count+1;
else count<=count-1;
 

Attachments

Thread Starter

PG1995

Joined Apr 15, 2011
832
Thank you.

First things first. I simulated your shift register, and it workd as expected. See insert.
Yes, that's good. It looks like you used Xilinx. I use Verilogger Pro and my code is still not working. Anyway, it's good to see it's fine otherwise.

Your counter will never load the starting value because your structure is incorrect. It should look like this:
I have followed your suggestions but it's still not working. Please have a look and kindly let me know where I went wrong.

Rich (BB code):
// 3-bit up/down counter

module up_down_counter(count,data_in,clk,rst,counter_on,count_up,load);

	input [2:0]data_in;
	input clk,rst,counter_on,count_up,load;
	output [2:0]count;
	
	wire [2:0]data_in;
	wire clk,rst,counter_on,count_up,load;
	reg [2:0]count;
	
	always @(posedge clk or posedge rst) begin 
		if (rst==1) count<=3'bz;
		else if (load==1) count<=data_in;

		if(counter_on==1) begin
                if(count_up==1) count=count+1;
			else count=count-1;
			end
                     end
endmodule

// stimulus

module testbench;

	reg [2:0]data_in;
	reg clk,rst,counter_on,count_up,load;
	wire [2:0]count;
	up_down_counter up_down(count,data_in,clk,rst,counter_on,count_up,load);
		
		always begin
			clk = 0;
			#10 clk = 1;
			#10;
			end
	
		initial
			begin
				rst=1;
			#4 rst=0;
			#3 load=1; data_in=3; counter_on=0;
                     #8 rst=1; data_in=0;
			#8 rst=0; load=0; counter_on=1;count_up=1; 
                     #40 rst=1;
			#8 rst=0; load=0; counter_on=1;count_up=0;
			#40 $finish;
			end
endmodule
 

Attachments

Brownout

Joined Jan 10, 2012
2,390
Thank you.



Yes, that's good. It looks like you used Xilinx. I use Verilogger Pro and my code is still not working. Anyway, it's good to see it's fine otherwise.
I'm using ModelSim

I have followed your suggestions but it's still not working. Please have a look and kindly let me know where I went wrong.
Look at your waves and see what's happening. Don't just give up. I got your code to work by modifying the testbench.
 

Brownout

Joined Jan 10, 2012
2,390
PG1995, before you try to test any more circuits, you need to find out why verilogger isn't working for perfectly good code. It won't be possible to debug code if your simulator isn't working.

You can download a free version of ModelSim. You only need to say you are a student.
 
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