# Verilog Syntax error

#### sirius3

Joined May 30, 2013
5
I am using iverilog simulator for mac and when i run the file with extension .va, it says there is a syntax error for the statement " include discipline.h " The header file is in the same folder. This syntax runs normally otherwise. Could someone please help me out?

#### Brownout

Joined Jan 10, 2012
2,390
include "discipline.h" Notice the quotation marks.