My goal is to connect two modules together: RfileReceiver and RegFile
I did this by implementing a top level module to create instances for these modules. Below is a block diagram of the two modules.
The arrow pointing into RfileReceiver is a 7-bit output called "link" coming from another module. Below is the description of link's bits:
link[6]: starting bit
link[5] & link[4]: address
link[3],link[2],link[1],link[0]: data
I have the verilog code for modules RegFile and toplevel. My only question here is, how would I go about seperating the bits of the link input into RfileReceiver to accomplish the above description?
My idea right now is using a case statement. However, I do not know how to represent the particular bits for a given case. For instance, if link = 1011100, I would have:
case(link)
begin
link[5] & link[4]: address
link[3],link[2],link[1],link[0]: data
endcase
I tried googling for the correct Verilog syntax to represent the pseudocode above, but I can't seem to find a solution. Will someone please help me?
I did this by implementing a top level module to create instances for these modules. Below is a block diagram of the two modules.
The arrow pointing into RfileReceiver is a 7-bit output called "link" coming from another module. Below is the description of link's bits:
link[6]: starting bit
link[5] & link[4]: address
link[3],link[2],link[1],link[0]: data
I have the verilog code for modules RegFile and toplevel. My only question here is, how would I go about seperating the bits of the link input into RfileReceiver to accomplish the above description?
My idea right now is using a case statement. However, I do not know how to represent the particular bits for a given case. For instance, if link = 1011100, I would have:
case(link)
begin
link[5] & link[4]: address
link[3],link[2],link[1],link[0]: data
endcase
I tried googling for the correct Verilog syntax to represent the pseudocode above, but I can't seem to find a solution. Will someone please help me?
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